LIS3DSH - three-axis accelerometer
Description
Library for interfacing STMicroelectronics LIS3DSH three-axis accelerometer.
The LIS3DSH is an ultra-low-power high- performance three-axis linear accelerometer with an embedded state machine that can be programmed to implement autonomous applications.
- SPI interface with communication speed up to 10 MHz
- I2C interface with communication speed up to 400 kHz
- Programmable embedded state machines
OVERVIEW
LIS3DSH_Abstract:
This library can be used to handle STMicroelectronics LIS3DSH three-axis accelerometers.
Interfaces:1x SPI or 1x I2C 1x GPIO (Only when using the SPI interface)
The LIS3DSH is an ultra-low-power high- performance three-axis linear accelerometer with an embedded state machine that can be programmed to implement autonomous
applications.SPI interface with communication speed up to 10 MHz I2C interface with communication speed up to 400 kHz Programmable embedded state machines
LIS3DSH_How_to_use_SPI_mode:
/* Hardware setup */
const
{
PORT_SPI = 0, // The first SPI interface should be used.
PIN_CS = 0, // The first GPIO should be used for the CS signal
}
/* Handles for available sensors */
new hACC[TLIS3DSH_Handle]; // Handle to manage the TLIS3DSH
/* 1 sec. timer is used for the general program sequence */
#callback MainTimer()
{
new iX, iY, iZ; // g-forces read from the LIS3DSH
// Reads the g-forces [mg] for all 3 axes from the LIS3DSH
catch( LIS3DSH_ReadMeasurement(hACC, iX, iY, iZ) );
// Issues g-forces [mg] for all 3 axes via the watch panel
#watch("g-forces=x: %.3fg, y: %.3fg, z: %.3fg", iX/1000.0, iY/1000.0, iZ/1000.0);
}
main()
{
// inits the SPI interface
catch(rM2M_SpiInit(PORT_SPI, LIS3DSH_SPICLK, LIS3DSH_SPIMODE));
// Initializes SPI communication with the LIS3DSH and prepares the LIS3DSH for use
catch (LIS3DSH_Init(hACC, PIN_CS, PORT_SPI));
// Activates the LIS3DSH using the following configuration:
// Set output data rate (ODR) to 6.25 Hz (Power-On default = "Power Down")
// Output registers not updated until MSB and LSB have been read (Power-On default = continuous update)
// Enables X, Y, Z axes (Power-On default)
new config = LIS3DSH_CTRL4_ODR_6_25HZ | LIS3DSH_CTRL4_BDU | LIS3DSH_CTRL4_XYZ_EN;
catch(LIS3DSH_Enable(hACC, config));
// Initialisation of a cyclic sec. timer
setInterval(MainTimer, 1000);
}
LIS3DSH_How_to_use_I2C_mode:
/* Hardware setup */
const
{
PORT_I2C = 0, // The first I2C interface should be used.
CHIP_ADDR = LIS3DSH_I2C_ADR0, // I2C Address of the chip
// (depends on the logic level at the chip's SEL/SDO pin)
}
/* Handles for available sensors */
new hACC[TLIS3DSH_Handle]; // Handle to manage the TLIS3DSH
/* 1 sec. timer is used for the general program sequence */
#callback MainTimer()
{
new iX, iY, iZ; // g-forces read from the LIS3DSH
// Reads the g-forces [mg] for all 3 axes from the LIS3DSH
catch( LIS3DSH_ReadMeasurement(hACC, iX, iY, iZ) );
// Issues g-forces [mg] for all 3 axes via the watch panel
#watch("g-forces=x: %.3fg, y: %.3fg, z: %.3fg", iX/1000.0, iY/1000.0, iZ/1000.0);
}
main()
{
// Inits the I2C interface
catch( rM2M_I2cInit( PORT_I2C, LIS3DSH_I2C_CLOCK , 0));
// Initializes I2C communication with the LIS3DSH and prepares the LIS3DSH for use
catch (LIS3DSH_Init(hACC, _ , PORT_I2C, CHIP_ADDR ));
// Activates the LIS3DSH using the following configuration:
// Set output data rate (ODR) to 6.25 Hz (Power-On default = "Power Down")
// Output registers not updated until MSB and LSB have been read (Power-On default = continuous update)
// Enables X, Y, Z axes (Power-On default)
new config = LIS3DSH_CTRL4_ODR_6_25HZ | LIS3DSH_CTRL4_BDU | LIS3DSH_CTRL4_XYZ_EN;
catch(LIS3DSH_Enable(hACC, config));
// Initialisation of a cyclic sec. timer
setInterval(MainTimer, 1000);
}
BASIC
LIS3DSH_SPICLK -
typical SPI clock speed to be used
LIS3DSH_I2C_CLOCK -
typical I2C clock speed to be used (400kHz, I2C Fast-Mode)
LIS3DSH_SPIMODE -
configuration of clock polarity and clock phase for the LIS3DSH
LIS3DSH_I2C_ADRx:
Available LIS3DSH I2C addresses
LIS3DSH_I2C_ADR0 - Must be used if SEL/SDO Pin of the LIS3DSH is connected to the voltage supply
LIS3DSH_I2C_ADR1 - Must be used if SEL/SDO pin of the LIS3DSH is connected to ground
LIS3DSH_CTRL4_x:
CTRL4 configuration bits
LIS3DSH_CTRL4_ODR_x - bit 4-7: Output data rate and power mode selection
LIS3DSH_CTRL4_BDU - bit3: Block data update
0 - Continuous update (default)
1 - Output registers not updated until MSB and LSB have been read which avoids reading values related to different sample times.
LIS3DSH_CTRL4_XYZ_EN - bit0-2: Enables all three axis (default)
To activate the axes individually, use the following definitions:
LIS3DSH_CTRL4_Z_EN - bit2: Z-axis enable
0 - Z-axis disabled
1 - Z-axis enabled (default)
LIS3DSH_CTRL4_Y_EN - bit1: Y-axis enable
0 - Y-axis disabled
1 - Y-axis enabled (default)
LIS3DSH_CTRL4_X_EN - bit0: X-axis enable
0 - X-axis disabled
1 - X-axis enabled (default)
LIS3DSH_CTRL4_ODR_x:
Output data rate and power mode selection (CTRL4, bit 4-7)
LIS3DSH_CTRL4_ODR_POWER_DOWN - (0 << 4): Power down (default)
LIS3DSH_CTRL4_ODR_3_125HZ - (1 << 4): 3.125 Hz
LIS3DSH_CTRL4_ODR_6_25HZ - (2 << 4): 6.25 Hz
LIS3DSH_CTRL4_ODR_12_5HZ - (3 << 4): 12.5 Hz
LIS3DSH_CTRL4_ODR_25HZ - (4 << 4): 25 Hz
LIS3DSH_CTRL4_ODR_50HZ - (5 << 4): 50 Hz
LIS3DSH_CTRL4_ODR_100HZ - (6 << 4): 100 Hz
LIS3DSH_CTRL4_ODR_400HZ - (7 << 4): 400 Hz
LIS3DSH_CTRL4_ODR_800HZ - (8 << 4): 800 Hz
LIS3DSH_CTRL4_ODR_1600HZ - (9 << 4): 1600 Hz
LIS3DSH_Init(handle[TLIS3DSH_Handle], cs=-1, port, addr=-1)
Initializes communication with the LIS3DSH and prepares the LIS3DSH for use
In SPI mode (cs >= 0, addr =-1) first of all the used CS pin is configured as output and set to high so no data transfer takes place at the beginning. After that, regardless of the mode (SPI or I2C), the device ID is read out. If the ID register check succeeds, the two read-only information registers are read out. If they are also correct (no error is returned), the ADD_INC bit in control register 6 is set so that the address used to read/write data is increased at every block. Moreover, the two state machines are disabled.
handle : TLIS3DSH_Handle - Empty device handle for a TLIS3DSH
cs : s32 - Pin used for the CS signal
-1 - I2C mode enabeld
>= 0 - Pin used for the CS signal (Only GPIO pins are supported, starting with 0 for the first GPIO of the device)
port : s32 - interface (SPI or I2C) where LIS3DSH is connected to
The interface must be initialisation before using rM2M_SpiInit() or rM2M_I2cInit().
addr : s32 - I2C Address of the chip
-1 - SPI mode enabeld
>= 0 - I2C Address of the chip (Use only the addresses specified under LIS3DSH_I2C_ADRx)
returns : s32
OK - if successful
ERROR - if one of the following errors occurs
< OK - if another error occurs
LIS3DSH_Enable(handle[TLIS3DSH_Handle], ctrl4 = LIS3DSH_CTRL4_ODR_6_25HZ | LIS3DSH_CTRL4_BDU | LIS3DSH_CTRL4_XYZ_EN )
Activates the LIS3DSH by setting the "CTRL4" register
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
ctrl4 : s32 - Control register 4 configuration (Output data rate / Block data update / Axis enable)
Use LIS3DSH_CTRL4_x configuration bits
returns : s32
OK - if successful
ERROR - If an error occurs
LIS3DSH_ReadMeasurement(handle[TLIS3DSH_Handle], &x, &y, &z)
Reads acceleration data in mg from the LIS3DSH
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
x : s32 - Buffer for storing the X-axis value [mg], unchanged if result < OK
y : s32 - Buffer for storing the Y-axis value [mg], unchanged if result < OK
z : s32 - Buffer for storing the Z-axis value [mg], unchanged if result < OK
returns : s32
OK - if successful
ERROR - Unexpected full-scale selection stored in controll register 5
< OK - if another error occurs
LIS3DSH_Disable(handle[TLIS3DSH_Handle])
Sets the LIS3DSH into power-down mode (i.e. no data sampling is performed) and thus grants minimum power consumption
When accessing the CTRL4 register, only the ODR bits are set to "Power-down". All other bits of the CTRL4 register remain unchanged.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
returns : s32
OK - if successful
ERROR - if one of the following errors occurs
EXPERT
LIS3DSH_SPICLK_MAX -
absolute maximum SPI clock speed (10MHz)
LIS3DSH_I2C_CLOCK_MAX -
absolute maximum I2C clock speed
LIS3DSH_REG_x:
Available register (Address | R/W | Default | Description)
LIS3DSH_REG_OUT_T - 0x0C | R | --- |
8-bit temperature output register. The resolution is 1 LSB/deg and 00h corresponds to 25 degrees Celsius.
LIS3DSH_REG_INFO1 - 0x0D | R | 0x21 |
Information Register 1. Its value is fixed at 0x21.
LIS3DSH_REG_INFO2 - 0x0E | R | 0x00 |
Information Register 2. Its value is fixed at 0x00.
LIS3DSH_REG_WHO_AM_I - 0x0F | R | 0x3F |
Device identification register.
LIS3DSH_REG_OFF_X - 0x10 | R/W | 0x00 |
X-axis offset compensation register
Output(axis) = Measurement(axis) - OFFSET(axis) * 32
Thus, the offset on each axis can be compensated from -4095 to 4096 LSB, with steps of 32 LSB.
LIS3DSH_REG_OFF_Y - 0x11 | R/W | 0x00 |
Y-axis offset compensation register (see LIS3DSH_REG_OFF_X for details)
LIS3DSH_REG_OFF_Z - 0x12 | R/W | 0x00 |
Z-axis offset compensation register (see LIS3DSH_REG_OFF_X for details)
LIS3DSH_REG_CS_X - 0x13 | R/W | 0x00 |
X-axis Constant Shift Register. This value acts as a temporary offset in DIFF-Mode for state machine 2 only
LIS3DSH_REG_CS_Y - 0x14 | R/W | 0x00 |
Y-axis Constant Shift Register. This value acts as a temporary offset in DIFF-Mode for state machine 2 only
LIS3DSH_REG_CS_Z - 0x15 | R/W | 0x00 |
Z-axis Constant Shift Register. This value acts as a temporary offset in DIFF-Mode for state machine 2 only
LIS3DSH_REG_LC - 0x16 | R/W | 0x0001 |
16-bit long-counter register for interrupt state machine program timing.-1: Not valid value, counting stopped 0: Counter full: interrupt available and counter is set to default > 0: counting
LIS3DSH_REG_STAT - 0x18 | R | 0x00 |
Interrupt status - interrupt synchronization register (See LIS3DSH_REG_STAT_x).
LIS3DSH_REG_PEAK1 - 0x19 | R | 0x00 |
Peak value for state machine 1. It stores the highest absolute peak value detected. The peak value is reset when the REL state machine command occurs or a new initial start occurs.
LIS3DSH_REG_PEAK2 - 0x1A | R | 0x00 |
Peak value for state machine 2. (see LIS3DSH_REG_PEAK1 for details)
LIS3DSH_REG_VFC_1 - 0x1B | R/W | 0x00 |
Vector filter coefficients 1 register for diff. filter.
The vector filter is a 7th-order anti-symmetric FIR filter. The 8 taps have a 4x2 structure:
VFC_1, VFC_2, VFC_3, VFC_4 and -VFC_1, -VFC_2, -VFC_3, -VFC_4.
The vector filter can be enabled or disabled by the VFILT bit in the CTRL3 register.
LIS3DSH_REG_VFC_2 - 0x1C | R/W | 0x00 |
Vector filter coefficients 2 register for diff. filter (see LIS3DSH_REG_VFC_1 for details)
LIS3DSH_REG_VFC_3 - 0x1D | R/W | 0x00 |
Vector filter coefficients 3 register for diff. filter (see LIS3DSH_REG_VFC_1 for details)
LIS3DSH_REG_VFC_4 - 0x1E | R/W | 0x00 |
Vector filter coefficients 4 register for diff. filter (see LIS3DSH_REG_VFC_1 for details)
LIS3DSH_REG_THRS3 - 0x1F | R/W | 0x00 |
Common threshold for overrun detection. The value is always unsigned (ABS) regardless of the ABS settings in the LIS3DSH_REG_SETT1/LIS3DSH_REG_SETT2 registers. So, the THRS3 value is symmetric
to the zero level. When the acceleration of any axis exceeds the THRS3 limit, the state machines are
reset (program pointer address = reset pointer address). The reset of the state machines is enabled
through the THR3_xA bits in the LIS3DSH_REG_SETT1/LIS3DSH_REG_SETT2 registers.
LIS3DSH_REG_CTRL4 - 0x20 | R/W | 0x07 |
Control Register 4 (use LIS3DSH_Enable(), see also LIS3DSH_CTRL4_x)
LIS3DSH_REG_CTRL1 - 0x21 | R/W | 0x00 |
Control Register 1 (State machine 1 interrupt configuration register, see LIS3DSH_CTRL1_x )
LIS3DSH_REG_CTRL2 - 0x22 | R/W | 0x00 |
Control Register 2 (State machine 2 interrupt configuration register, see LIS3DSH_CTRL2_x )
LIS3DSH_REG_CTRL3 - 0x23 | R/W | 0x00 |
Control Register 3 (see LIS3DSH_CTRL3_x)
LIS3DSH_REG_CTRL5 - 0x24 | R/W | 0x00 |
Control Register 5 (see LIS3DSH_CTRL5_x)
LIS3DSH_REG_CTRL6 - 0x25 | R/W | 0x10 |
Control Register 6 (see LIS3DSH_CTRL6_x)
LIS3DSH_REG_STATUS - 0x27 | R | 0x00 |
Status data register (see LIS3DSH_REG_STATUS_x)
LIS3DSH_REG_OUT_X - 0x28 | R | --- |
X-axis acceleration data (16-bit, use LIS3DSH_ReadMeasurement())
LIS3DSH_REG_OUT_Y - 0x2A | R | --- |
Y-axis acceleration data (16-bit, use LIS3DSH_ReadMeasurement())
LIS3DSH_REG_OUT_Z - 0x2C | R | --- |
Z-axis acceleration data (16-bit, use LIS3DSH_ReadMeasurement())
LIS3DSH_REG_FIFO_CTRL - 0x2E | R/W | 0x00 |
FIFO control register (see LIS3DSH_REG_FIFO_CTRL_x)
LIS3DSH_REG_FIFO_SRC - 0x2F | R | --- |
FIFO SRC control register (see LIS3DSH_REG_FIFO_SRC_x)
LIS3DSH_REG_ST1_X - 0x40 - 0x4F | W | --- |
State machine 1 code register
State machine 1 system register is made up of 16, 8-bit registers to implement 16-step op-code (Use LIS3DSH_LoadStateMachine()).
LIS3DSH_REG_TIM4_1 - 0x50 | W | 0x00 |
8-bit unsigned initial value "TIM4_1" for Timer Counter 1 (TC1)
LIS3DSH_REG_TIM3_1 - 0x51 | W | 0x00 |
8-bit unsigned initial value "TIM3_1" for Timer Counter 1 (TC1)
LIS3DSH_REG_TIM2_1 - 0x52 | W | 0x0000 |
16-bit unsigned initial value "TIM2_1" for Timer Counter 1 (TC1)
LIS3DSH_REG_TIM1_1 - 0x54 | W | 0x000 |
16-bit unsigned initial value "TIM1_1" for Timer Counter 1 (TC1)
LIS3DSH_REG_THRS2_1 - 0x56 | W | 0x00 |
Threshold value 1 for state machine 1 conditions.
LIS3DSH_REG_THRS1_1 - 0x57 | W | 0x00 |
Threshold value 2 for state machine 1 conditions.
LIS3DSH_REG_MASK1_B - 0x59 | W | --- |
Axis and sign mask (swap) for state machine 1 motion-detection operations (see LIS3DSH_REG_MASK_x)
LIS3DSH_REG_MASK1_A - 0x5A | W | --- |
Axis and sign mask (swap) for state machine 1 motion-detection operations (see LIS3DSH_REG_MASK_x)
LIS3DSH_REG_SETT1 - 0x5B | W | 0x00 |
Setting of threshold, peak detection, and flags for state machine 1 motion-detection operations (see LIS3DSH_REG_SETT_x)
LIS3DSH_REG_PR1 - 0x5C | R | --- |
Program and reset pointers for State Machine 1 (see LIS3DSH_REG_PR_x)
LIS3DSH_REG_TC1 - 0x5D | R | 0x0000 |
16-bit general timer counter for State Machine 1. Registers TIM1_1 (54h-55h), TIM2_1 (52h-53h), TIM3_1 (51h), and TIM4_1 (50h) define the initial value of the Timer Counter 1.
LIS3DSH_REG_OUTS1 - 0x5F | R | --- |
Output flags on axis for State Machine 1 management. Reading this register affects the interrupt release function.After reading OUTS1, the value is set to default (00h). See LIS3DSH_REG_OUTS_x
LIS3DSH_REG_ST2_X - 0x60 - 0x6F | W | --- |
State machine 2 code register
State machine 2 system register is made up of 16, 8-bit registers to implement 16-step op-code (Use LIS3DSH_LoadStateMachine()).
LIS3DSH_REG_TIM4_2 - 0x70 | W | 0x00 |
8-bit unsigned initial value "TIM4_2" for Timer Counter 2 (TC2)
LIS3DSH_REG_TIM3_2 - 0x71 | W | 0x00 |
8-bit unsigned initial value "TIM3_2" for Timer Counter 2 (TC2)
LIS3DSH_REG_TIM2_2 - 0x72 | W | 0x0000 |
16-bit unsigned initial value "TIM2_2" for Timer Counter 2 (TC2)
LIS3DSH_REG_TIM1_2 - 0x74 | W | 0x0000 |
16-bit unsigned initial value "TIM1_2" for Timer Counter 2 (TC2)
LIS3DSH_REG_THRS2_2 - 0x76 | W | 0x00 |
Threshold value 1 for state machine 2 conditions.
LIS3DSH_REG_THRS1_2 - 0x77 | W | 0x00 |
Threshold value 2 for state machine 2 conditions.
LIS3DSH_REG_DES2 - 0x78 | w | 0x00 |
Decimation counter value for State Machine 2
LIS3DSH_REG_MASK2_B - 0x79 | W | --- |
Axis and sign mask (swap) for state machine 2 motion-detection operations (see LIS3DSH_REG_MASK_x)
LIS3DSH_REG_MASK2_A - 0x7A | W | 0x |
Axis and sign mask (swap) for state machine 2 motion-detection operations (see LIS3DSH_REG_MASK_x)
LIS3DSH_REG_SETT2 - 0x7B | W | --- |
Setting of threshold, peak detection, and flags for state machine 2 motion-detection operations (see LIS3DSH_REG_SETT_x)
LIS3DSH_REG_PR2 - 0x7C | R | 0x |
Program and reset pointers for State Machine 2 (see LIS3DSH_REG_PR_x)
LIS3DSH_REG_TC2 - 0x7D | R | 0x0000 |
16-bit general timer counter for State Machine 12. Registers TIM1_2 (74h-75h), TIM2_2 (72h-73h), TIM3_2 (71h), and TIM4_2 (70h) define the initial value of the Timer Counter 2.
LIS3DSH_REG_OUTS2 - 0x7F | R | --- |
Output flags on axis for State Machine 2 management. Reading this register affects the interrupt release function.After reading OUTS2, the value is set to default (00h). See LIS3DSH_REG_OUTS_x
LIS3DSH_REG_STAT_x:
Interrupt status - interrupt synchronization register bits
LIS3DSH_REG_STAT_LONG - bit7: Interrupt flag to indicate that the long counter has expired.
0 - No interrupt
1 - Long counter interrupt flag.
Common to both state machines. LONG flag is reset to default value by reading the LC registers (LIS3DSH_REG_LC).
LIS3DSH_REG_STAT_SYNCW - bit6: Common information for OUTW (“output command and acknowledge from host” state machine command). Waiting on action from host.
0 - No action waiting from host
1 - Host action is waiting after OUTW command
This bit is reset to 0 whenever LIS3DSH_REG_OUTS1/LIS3DSH_REG_OUTS2 is read.
LIS3DSH_REG_STAT_SYNC1 - bit5: State machine 1 sync state
0 - State machine 1 running normally
1 - State machine 1 stopped and waiting for restart request from state machine 2
LIS3DSH_REG_STAT_SYNC2 - bit4: State machine 2 sync state
0 - State machine 2 running normally
1 - State machine 2 stopped and waiting for restart request from state machine 1
LIS3DSH_REG_STAT_INT_SM1 - bit3: State machine 1 interrupt state
0 - No interrupt on state machine 1
1 - State machine 1 interrupt occurred.
The interrupt signal is reset when the LIS3DSH_REG_OUTS1 register is read.
LIS3DSH_REG_STAT_INT_SM2 - bit2: State machine 2 interrupt state
0 - No interrupt on state machine 2
1 - State machine 2 interrupt occurred.
The interrupt signal is reset when the LIS3DSH_REG_OUTS2 register is read.
LIS3DSH_REG_STAT_DOR - bit1: The Data OverRun bit indicates when a new set of data has overwritten the previous set in the output registers.
0 - No overrun
1 - Data overrun
The overrun bit is automatically cleared when data are read and no new data have been produced in the meantime.
LIS3DSH_REG_STAT_DRDY - bit0: New data are ready in the output registers
0 - Data not ready
1 - Data ready
LIS3DSH_CTRL1_x:
CTRL1 configuration bits
LIS3DSH_CTRL1_HYST1_x - bit 5-7: Hysteresis (unsigned value, default = 0) which is added or subtracted from the threshold values (THRS1_1 and THRS2_1) of State Machine 1. The hysteresis value is added
or subtracted according to the condition to evaluate. (Use LIS3DSH_CTRL1_HYST1_0 to LIS3DSH_CTRL1_HYST1_7)
LIS3DSH_CTRL1_SM1_PIN - bit3: Specifies to which interrupt pin the interrupt of the state machine 1 is routed.
0 - State Machine 1 interrupt routed to INT1. (default)
1 - State Machine 1 interrupt routed to INT2.
LIS3DSH_CTRL1_SM1_EN - bit0: State of state machine 1
0 - State Machine 1 disabled. Temporary memories and registers related to this state machine are left intact. (default)
1 - State Machine 1 enabled.
LIS3DSH_CTRL2_x:
CTRL2 configuration bits
LIS3DSH_CTRL2_HYST2_x - bit 5-7: Hysteresis (unsigned value, default = 0) which is added or subtracted from the threshold values (THRS1_2 and THRS2_2) of State Machine 2. The hysteresis value is added
or subtracted according to the condition to evaluate. (Use LIS3DSH_CTRL2_HYST2_0 to LIS3DSH_CTRL2_HYST2_7)
LIS3DSH_CTRL2_SM2_PIN - bit3: Specifies to which interrupt pin the interrupt of the state machine 2 is routed.
0 - State Machine 2 interrupt routed to INT1. (default)
1 - State Machine 2 interrupt routed to INT2.
LIS3DSH_CTRL2_SM2_EN - bit0: State of state machine 1
0 - State Machine 2 disabled. Temporary memories and registers related to this state machine are left intact. (default)
1 - State Machine 2 enabled.
LIS3DSH_CTRL3_x:
CTRL3 configuration bits
LIS3DSH_CTRL3_DR_EN - bit7: Data-ready interrupt enable
0 - Data-ready interrupt disabled (default)
1 - Data-ready interrupt enabled and routed to INT1
LIS3DSH_CTRL3_IEA - bit6: Interrupt signal polarity
0 - Interrupt signal active LOW (default)
1 - Interrupt signal active HIGH.
LIS3DSH_CTRL3_IEL - bit5: Interrupt signal latching
0 - Interrupt signal latched (default)
1 - Interrupt signal pulsed
LIS3DSH_CTRL3_INT2_EN - bit4: Interrupt 2 enable/disable
0 - INT2 signal disabled (High-Z state) (default)
1 - INT2 signal enabled (signal pin fully functional).
LIS3DSH_CTRL3_INT1_EN - bit3: Interrupt 2 enable/disable.
0 - INT1/DRDY signal disabled (High-Z state) (default)
1 - INT1/DRDY signal enabled (signal pin fully functional)
DR_EN bit in CTRL3 register should be taken into account too.
LIS3DSH_CTRL3_VFILT - bit2: Vector filter enable/disable.
0 - Vector filter disabled (default)
1 - Vector filter enabled
LIS3DSH_CTRL3_STRT - bit0: Soft reset bit
0 - No soft reset (default)
1 - Resets the whole internal logic circuitry (POR function) when set to 1. It automatically returns to 0
LIS3DSH_CTRL5_x:
CTRL5 configuration bits
LIS3DSH_CTRL5_BW_x - bit 6-7: Anti-aliasing filter bandwidth
LIS3DSH_CTRL5_FSCALE_x - bit 3-5: Full-scale selection
LIS3DSH_CTRL5_ST_x - bit 1-2: Self-test enable
LIS3DSH_CTRL5_BW_x:
Anti-aliasing filter bandwidth (CTRL5, bit 6-7)
LIS3DSH_CTRL5_BW_800HZ - (0 << 6): 800 Hz (default)
LIS3DSH_CTRL5_BW_200HZ - (1 << 6): 200 Hz
LIS3DSH_CTRL5_BW_400HZ - (2 << 6): 400 Hz
LIS3DSH_CTRL5_BW_50 - (3 << 6): 50 Hz
LIS3DSH_CTRL5_FSCALE_x:
Full-scale selection (CTRL5, bit 3-5)
LIS3DSH_CTRL5_FSCALE_2G - (0 << 3): ±2g (default)
LIS3DSH_CTRL5_FSCALE_4G - (1 << 3): ±4g
LIS3DSH_CTRL5_FSCALE_6G - (2 << 3): ±6g
LIS3DSH_CTRL5_FSCALE_8G - (3 << 3): ±8g
LIS3DSH_CTRL5_FSCALE_16G - (4 << 3): ±16g
LIS3DSH_CTRL5_ST_x:
elf-test enable (CTRL5, bit 1-2)
LIS3DSH_CTRL5_ST_NORMAL_MODE - (0 << 1): Normal mode (default)
LIS3DSH_CTRL5_ST_POSITIV_SIGN - (1 << 1): Positive sign self-test
LIS3DSH_CTRL5_ST_NEGATIVE_SIGN - (2 << 1): Not Allowed
LIS3DSH_CTRL6_x:
CTRL6 configuration bits
LIS3DSH_CTRL6_BOOT - bit7: Force reboot
0 - No reboot (default)
1 - Force reboot, cleared as soon as the reboot is finished. Active high.
LIS3DSH_CTRL6_FIFO_EN - bit6: FIFO enable
0 - Disabled (default)
1 - Enabeld
LIS3DSH_CTRL6_WTM_EN - bit5: Stop on watermark - FIFO depth can be limited at the watermark value by setting to “1” the WTM_EN bit
0 - Disabled (default)
1 - Enabeld
LIS3DSH_CTRL6_ADD_INC - bit4: Register address automatically increased during a multiple byte access with a serial interface (I2C or SPI).
0 - Disabled
1 - Enabeld (default)
LIS3DSH_CTRL6_P1_EMPTY - bit3: Enable FIFO empty indication on INT1 pin.
0 - Disabled (default)
1 - Enabeld
LIS3DSH_CTRL6_P1_WTM - bit2: FIFO watermark interrupt on INT1 pin.
0 - Disabled (default)
1 - Enabeld
LIS3DSH_CTRL6_P1_OVERRUN - bit1: FIFO overrun interrupt on INT1 pin.
0 - Disabled (default)
1 - Enabeld
LIS3DSH_CTRL6_P1_BOOT - bit0: Boot interrupt on INT2 pin.
0 - Disabled (default)
1 - Enabeld
LIS3DSH_REG_STATUS_x:
Status data register bits
LIS3DSH_REG_STATUS_ZYXOR - bit7: X-, Y- and Z-axis data overrun
0 - No overrun has occurred (default)
1 - A new set of data has overwritten the previous set
LIS3DSH_REG_STATUS_ZOR - bit6: Z-axis data overrun
0 - No overrun has occurred (default)
1 - New data for the Z-axis has overwritten the previous data
LIS3DSH_REG_STATUS_YOR - bit5: Y-axis data overrun
0 - No overrun has occurred (default)
1 - New data for the Y-axis has overwritten the previous data
LIS3DSH_REG_STATUS_XOR - bit4: X-axis data overrun
0 - No overrun has occurred (default)
1 - New data for the X-axis has overwritten the previous data
LIS3DSH_REG_STATUS_ZYXDA - bit3: X-, Y- and Z-axis new data available
0 - A new set of data is not yet available (default)
1 - A new set of data is available
LIS3DSH_REG_STATUS_ZDA - bit2: Z-axis new data available
0 - New data for the Z-axis is not yet available (default)
1 - New data for Z-axis is available
LIS3DSH_REG_STATUS_YDA - bit1: Y-axis new data available
0 - New data for the Y-axis is not yet available (default)
1 - New data for Y-axis is available
LIS3DSH_REG_STATUS_XDA - bit0: X-axis new data available
0 - New data for the X-axis is not yet available (default)
1 - New data for X-axis is available
LIS3DSH_REG_FIFO_CTRL_x:
FIFO control register configuration bits
LIS3DSH_REG_FIFO_CTRL_FM_x - bit 5-7: FIFO mode selection
LIS3DSH_REG_FIFO_CTRL_WTMP_X - bit 0-4: FIFO watermark pointer; FIFO deep if the watermark is enabled (Use 0x00 t0 0x1F).
LIS3DSH_REG_FIFO_CTRL_FM_x:
FIFO mode selection (FIFO_CTRL, bit 5-7)
LIS3DSH_REG_FIFO_CTRL_FM_BYPASS - (0 << 5): Bypass mode. FIFO turned off.
LIS3DSH_REG_FIFO_CTRL_FM_FIFO - (1 << 5): FIFO mode. Stops collecting data when FIFO is full.
LIS3DSH_REG_FIFO_CTRL_FM_STREAM - (2 << 5): Stream mode. If the FIFO is full, the new sample overwrites the older one (circular buffer).
LIS3DSH_REG_FIFO_CTRL_FM_S_TO_F - (3 << 5): Stream mode until trigger is de-asserted, then FIFO mode.
LIS3DSH_REG_FIFO_CTRL_FM_B_TO_S - (4 << 5): Bypass mode until trigger is de-asserted, then Stream mode.
LIS3DSH_REG_FIFO_CTRL_FM_B_TO_F - (7 << 5): Bypass mode until trigger is de-asserted, then FIFO mode.
LIS3DSH_REG_FIFO_SRC_x:
FIFO SRC control register bits
LIS3DSH_REG_FIFO_SRC_WTM - bit7: Watermark status
0 - FIFO filling is lower than WTM level
1 - FIFO filling is equal to or higher than WTM level
LIS3DSH_REG_FIFO_SRC_OVRN_FIFO - bit6: Overrun bit status
0 - FIFO is not completely filled
1 - FIFO is completely filled
LIS3DSH_REG_FIFO_SRC_EMPTY - bit5: FIFO empty bit status
0 - FIFO not empty
1 - FIFO empty
LIS3DSH_REG_FIFO_SRC_FSS_MSK - bit 0-4: Number of samples stored in the FIFO - 1
LIS3DSH_REG_MASK_x:
MASK1_B, MASK1_A, MASK2_B and MASK2_A register configuration bits
LIS3DSH_REG_MASK_P_X - bit7:
0 - X+ disabled
1 - X+ enabled
LIS3DSH_REG_MASK_N_X - bit6:
0 - X- disabled
1 - X- enabled
LIS3DSH_REG_MASK_P_Y - bit5:
0 - Y+ disabled
1 - Y+ enabled
LIS3DSH_REG_MASK_N_Y - bit4:
0 - Y- disabled
1 - Y- enabled
LIS3DSH_REG_MASK_P_Z - bit3:
0 - Z+ disabled
1 - Z+ enabled
LIS3DSH_REG_MASK_N_Z - bit2:
0 - Z- disabled
1 - Z- enabled
LIS3DSH_REG_MASK_P_V - bit1:
0 - V+ disabled
1 - V+ enabled
LIS3DSH_REG_MASK_N_V - bit0:
0 - V- disabled
1 - V- enabled
LIS3DSH_REG_SETT_x:
SETT1/SETT2 register configuration bits
LIS3DSH_REG_SETT_P_DET - bit7: State machine peak detection
0 - Peak detection disabled (default)
1 - Peak detection enabled
LIS3DSH_REG_SETT_THR3_SA - bit6: Enables the function that when the acceleration of any axis exceeds the THRS3 limit, the state machines is reset.
0 - No action (default)
1 - Threshold 3 enabled for axis and sign mask reset (MASKB_x)
LIS3DSH_REG_SETT_ABS - bit5: Specifies whether signed or unsigned thresholds are used
0 - unsigned thresholds THRSx (thresholds are symmetric to the zero level) (default)
1 - signed thresholds THRSx (thresholds are sign dependent )
LIS3DSH_REG_SETT_RADI - bit4: Only available on SETT2
0 - Raw data
1 - Diff. data for State Machine 2
LIS3DSH_REG_SETT_D_CS - bit3: Only available on SETT2
0 - DIFF2 enabled (difference between current data and previous data)
1 - Constant shift enabled (difference between current data and constant values)
LIS3DSH_REG_SETT_THR3_MA - bit2: Enables the function that when the acceleration of any axis exceeds the THRS3 limit, the state machines is reset.
0 - No action (default)
1 - Threshold 3 enabled for axis and sign mask reset (MASKA_x)
LIS3DSH_REG_SETT_R_TAM - bit1: Next condition validation flag
0 - Mask frozen on the axis that triggers the condition (default)
1 - Standard mask always evaluated
LIS3DSH_REG_SETT_SITR - bit0:
0 - No action (default)
1 - STOP and CONT state machine commands generate an interrupt and perform output actions as OUTC state machine command.
LIS3DSH_REG_PR_x:
PR1/PR2 register bits
LIS3DSH_REG_PR_RP_MSK - bit 4-7: Reset pointer address
LIS3DSH_REG_PR_PP_MSK - bit 0-3: Program pointer address
LIS3DSH_REG_OUTS_x:
OUTS1/OUTS2 register bits
LIS3DSH_REG_OUTS_P_X - bit7:
0 - X+ not shown
1 - X+ shown
LIS3DSH_REG_OUTS_N_X - bit6:
0 - X- not shown
1 - X- shown
LIS3DSH_REG_OUTS_P_Y - bit5:
0 - Y+ not shown
1 - Y+ shown
LIS3DSH_REG_OUTS_N_Y - bit4:
0 - Y- not shown
1 - Y- shown
LIS3DSH_REG_OUTS_P_Z - bit3:
0 - Z+ not shown
1 - Z+ shown
LIS3DSH_REG_OUTS_N_Z - bit2:
0 - Z- not shown
1 - Z- shown
LIS3DSH_REG_OUTS_P_V - bit1:
0 - V+ not shown
1 - V+ shown
LIS3DSH_REG_OUTS_N_V - bit0:
0 - V- not shown
1 - V- shown
LIS3DSH_STATE_MACHINE_x:
Available state machines
LIS3DSH_STATE_MACHINE_1 - Use state machines 1
LIS3DSH_STATE_MACHINE_2 - Use state machines 2
LIS3DSH_SM_x:
State machine register offsets
LIS3DSH_SM_TIM4 - (0x0) 8-bit unsigned initial value "TIM4_x" for Timer Counter x (TCx)
LIS3DSH_SM_TIM3 - (0x1) 8-bit unsigned initial value "TIM3_x" for Timer Counter x (TCx)
LIS3DSH_SM_TIM2_L - (0x2) Low byte of 16-bit unsigned initial value "TIM2_x" for Timer Counter x (TCx)
LIS3DSH_SM_TIM2_H - (0x3) High byte of 16-bit unsigned initial value "TIM2_x" for Timer Counter x (TCx)
LIS3DSH_SM_TIM1_L - (0x4) Low byte of 16-bit unsigned initial value "TIM1_x" for Timer Counter x (TCx)
LIS3DSH_SM_TIM1_H - (0x5) High byte of 16-bit unsigned initial value "TIM1_x" for Timer Counter x (TCx)
LIS3DSH_SM_THRS2 - (0x6) Threshold value 1 for state machine conditions. Data are in two’s complement.
LIS3DSH_SM_THRS1 - (0x7) Threshold value 2 for state machine conditions. Data are in two’s complement.
LIS3DSH_SM_DES - (0x8) Decimation counter value for state machine ( only for state machine 2 !)
LIS3DSH_SM_MASK_B - (0x9) Axis and sign mask (swap) for state machine motion-detection operations.
LIS3DSH_SM_MASK_A - (0xA) Axis and sign mask (swap) for state machine motion-detection operations.
LIS3DSH_SM_SETT - (0xB) Setting of threshold, peak detection, and flags for state machine motion-detection operations.
TLIS3DSH_InitRegs:
Contains state machine register information
reg_ofs - Offset of a state machine register (LIS3DSH_SM_x)
value - Value of a state machine register
LIS3DSH_Read(handle[TLIS3DSH_Handle], iRegInfo, &iData)
Reads register of LIS3DSH
Use this function to read unsigned 8-Bit, signed 8-Bit, unsigned 16-Bit or signed 16-Bit registers of the LIS3DSH. The read data is unpacked according to the data type in the register information
variable.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
iRegInfo : s32 - Register information contains address and data type (Use LIS3DSH_REG_x)
iData : s32 - Variable for storing the data read from the LIS3DSH
returns : s32
OK - if successful
ERROR - if one of the following errors occurs
< OK - if another error occurs
LIS3DSH_ReadBuf(handle[TLIS3DSH_Handle], iRegInfo, aData{}, iLen)
Reads raw data from a number of LIS3DSH registers
Use this function to read a defined number of registers from the LIS3DSH. The data is given back as packed array.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
iRegInfo : s32 - Address of the register from which onwards the data should be read (Use LIS3DSH_REG_x)
aData : {} - Byte array for storing the raw data read from the LIS3DSH
iLen : s32 - Number of bytes to be read
returns : s32
OK - if successful
ERROR - Number of bytes to be read >255
< OK - if another error occurs
LIS3DSH_Write(handle[TLIS3DSH_Handle], iRegInfo, iData)
Writes register of LIS3DSH
Use this function to write unsigned 8-Bit, signed 8-Bit, unsigned 16-Bit or signed 16-Bit registers of the LIS3DSH. The data to be written is packed according to the data type in the register information
variable and sent to the sensor.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
iRegInfo : s32 - Register information contains address and data type (Use LIS3DSH_REG_x)
iData : s32 - Data to be packed and written to the LIS3DSH
returns : s32
OK - if successful
ERROR - if one of the following errors occurs
< OK - if another error occurs
LIS3DSH_WriteBuf(handle[TLIS3DSH_Handle], iRegInfo, aData{}, iLen)
Writes a number of LIS3DSH registers
Use this function to write a defined number of LIS3DSH registers. The data needs to be given to the function as a packed array
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
iRegInfo : s32 - Address of the register from which onwards the data should be written (Use LIS3DSH_REG_x)
aData{} - Byte array containing the data to be written to the registers of the LIS3DSH
iLen : s32 - Number of bytes to be written
returns : s32
OK - if successful
ERROR - Number of bytes to be written >255
< OK - if another error occurs
LIS3DSH_ReadMeasurementRaw(handle[TLIS3DSH_Handle], &x, &y, &z)
Reads raw acceleration data from the LIS3DSH
The function reads and buffers the raw output values of X- Y- and Z-axis. Output data of one axis consists of two bytes. The rM2M_Pack() function provides access to packed data and allows
to store the packed values in another variable. This stored data is accessed by reference.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
x : s32 - Buffer for storing the X-axis raw value, unchanged if result < OK
y : s32 - Buffer for storing the Y-axis raw value, unchanged if result < OK
z : s32 - Buffer for storing the Z-axis raw value, unchanged if result < OK
returns : s32
OK - if successful
< OK - if an error occurs
LIS3DSH_LoadStateMachine(handle[TLIS3DSH_Handle], sm, code{16}, const init_regs[][TLIS3DSH_InitRegs])
Enables state machine
The function detects at first which state machine should be used (1 or 2) and initialises the associated register addresses. After disabling the state machine, the 16-byte code is handed over to the LIS3DSH_WriteBuf() function. Additional state machine registers are then also initialised. See the LIS3DSH datasheet for further information. When the process is finished, the state machine is enabled.
To enable/disable the state machine the SMx_EN bit in the corresponding register (CTRL1 or CTRL2) is toggled. All other bits of the register remain unchanged.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
sm : s32 - Indicates which of the two state machines should be enabled (Use LIS3DSH_STATE_MACHINE_x)
code : {} - 16 step op-code which should be written to the LIS3DSH
init_regs : [][TLIS3DSH_InitRegs] - Array of structures that contain additional state machine register information which should be written to the LIS3DSH
As the number of array elements of the first level is variable, the array must be terminated with [-1, -1]. See example below.
static aLIS3DSH_InitRegs[][TLIS3DSH_InitRegs] =
[
[LIS3DSH_SM_THRS1, 0x02],
[LIS3DSH_SM_MASK_B, 0xFC],
[LIS3DSH_SM_MASK_A, 0xFC],
[LIS3DSH_SM_SETT, 0x11],
[-1, -1]
];
returns : s32
OK - if successful
ERROR - Invalid state machine selected
< OK - if another error occurs
LIS3DSH_DisableStateMachine(handle[TLIS3DSH_Handle], sm)
Disables state machine
The function detects which state machine should be disabled and then clears the SMx_EN bit in the corresponding register (CTRL1 or CTRL2). All other bits of the register remain unchanged.
handle : TLIS3DSH_Handle - Device handle of a specific LIS3DSH (Initialized by LIS3DSH_Init() )
sm : s32 - Indicates which of the two state machines should be enabled (Use LIS3DSH_STATE_MACHINE_x)
returns : s32
OK - if successful
ERROR - Invalid state machine selected
< OK - if another error occurs