LIS2DH - three-axis accelerometer

Description

Library for interfacing STMicroelectronics LIS2DH three-axis accelerometer

The LIS2DH is an ultra-low-power high- performance three-axis linear accelerometer. -) I2C interface with communication speed up to 400 kHz

OVERVIEW

LIS2DH_Abstract:
This library can be used to handle STMicroelectronics LIS2DH three-axis accelerometers.

Interface: I2C

The LIS2DH is an ultra low-power high performance three-axis linear accelerometer.

The LIS2DH has dynamically user selectable full scales of ±2g/±4g/±8g/±16g and it is capable of measuring accelerations with output data rates from 1 Hz to 5.3 kHz

The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself.
LIS2DH_How_to_use:
/* Hardware setup */ const { PORT_I2C = 0, // The first I2C interface should be used. CHIP_ADDR = LIS2DH_I2C_ADDR0, // I2C Address of the chip // (depends on the logic level at the chip's SDO/SA0 pin) } /* Handles for available sensors */ new hACC[TLIS2DH_Handle]; // Handle to manage the TLIS2DH /* 1 sec. timer is used for the general program sequence */ #callback MainTimer() { new iX, iY, iZ; // g-forces read from the LIS2DH // Reads the g-forces [mg] for all 3 axes from the LIS2DH catch(LIS2DH_ReadMeasurement(hACC, iX, iY, iZ)); // Issues g-forces [mg] for all 3 axes via the watch panel #watch("g-forces=x: %0.3fg, y: %0.3fg, z: %0.3fg", iX/1000.0, iY/1000.0, iZ/1000.0); } /* Called up when the device has been prepared for the start of the application by the "salve" function */ #callback appInit() { // Inits the I2C interface catch(rM2M_I2cInit(PORT_I2C, LIS2DH_I2C_CLOCK, 0)); // Initializes I2C communication with the LIS2DH and prepares the LIS2DH for use catch(LIS2DH_Init(hACC, _ ,PORT_I2C, CHIP_ADDR)); // Activates the LIS2DH using the following configuration: // Set output data rate (ODR) to 5.376 kHz (Power-On default = "Power Down") // Enable Low Power mode (Power-On default = disabled) // Enables X, Y, Z axes (Power-On default) new ctrl1 = LIS2DH_CTRL1_ODR_LP_5376HZ | LIS2DH_CTRL1_LP_EN | LIS2DH_CTRL1_XYZ_EN; // Output registers not updated until MSB and LSB have been read (Power-On default = continuous update) // Setting full-scale to 2g (Power-On default) new ctrl4 = LIS2DH_CTRL4_BDU | LIS2DH_CTRL4_FSCALE_2G; catch(LIS2DH_Enable(hACC, ctrl1, ctrl4)); // Initialisation of a cyclic sec. timer setInterval(MainTimer, 1000); } /* Application entry point */ main() { salve( appInit); // Prepares device for application start (enable extended // debug interface, increase console buffer, say hello) }

BASIC

LIS2DH_I2C_CLOCK -

typical I2C clock speed to be used (400kHz, I2C Fast-Mode)

LIS2DH_I2C_ADDRx:

Available LIS2DH I2C addresses

LIS2DH_I2C_ADDR0 - Must be used if SDO/SA0 pin of the LIS2DH is connected to the voltage supply
LIS2DH_I2C_ADDR1 - Must be used if SDO/SA0 pin of the LIS2DH is connected to ground
LIS2DH_CTRL1_x:

CTRL1 configuration bits

LIS2DH_CTRL1_ODR_x - bit 4-7: Output data rate and power mode selection
LIS2DH_CTRL1_LP_EN - bit 3: Enable low power mode
0 - Normal mode (default)
1 - Low power mode
  • Normal mode is only active if CTRL1_LP_EN and CTRL4_HR of register LIS2DH_CTRL4_x are set to 0
  • CTRL1_LP_EN and CTRL4_HR must not be set at the same time
  • LIS2DH_CTRL1_XYZ_EN - bit0-2: Enables all three axis (default)
    To activate the axes individually, use the following definitions:
    LIS2DH_CTRL1_Z_EN - bit2: Z-axis enable
    0 - Z-axis disabled
    1 - Z-axis enabled (default)
    LIS2DH_CTRL1_Y_EN - bit1: Y-axis enable
    0 - Y-axis disabled
    1 - Y-axis enabled (default)
    LIS2DH_CTRL1_X_EN - bit0: X-axis enable
    0 - X-axis disabled
    1 - X-axis enabled (default)
    LIS2DH_CTRL1_ODR_x:

    Output data rate and power mode selection (CTRL1, bit 4-7)

    If not specified specifically, the output data rate can be used for all power modes
    LIS2DH_CTRL1_ODR_POWER_DOWN - (0 << 4): Power down (default)
    LIS2DH_CTRL1_ODR_1HZ - (1 << 4): 1 Hz
    LIS2DH_CTRL1_ODR_10HZ - (2 << 4): 10 Hz
    LIS2DH_CTRL1_ODR_25HZ - (3 << 4): 25 Hz
    LIS2DH_CTRL1_ODR_50HZ - (4 << 4): 50 Hz
    LIS2DH_CTRL1_ODR_100HZ - (5 << 4): 100 Hz
    LIS2DH_CTRL1_ODR_200HZ - (6 << 4): 200 Hz
    LIS2DH_CTRL1_ODR_400HZ - (7 << 4): 400 Hz
    LIS2DH_CTRL1_ODR_LP_1620HZ - (8 << 4): 1.620 kHz (only for low power mode)
    LIS2DH_CTRL1_ODR_HR_1344HZ - (9 << 4): 1.355 kHz (for normal/high resolution mode)
    LIS2DH_CTRL1_ODR_LP_5376HZ - (9 << 4): 5.376 kHz (only for low power mode)
    LIS2DH_CTRL1_ODR_MSK - (0x0F << 4): Output data rate and power mode selection bit mask
    LIS2DH_CTRL4_x:

    CTRL4 configuration bits

    LIS2DH_CTRL4_BDU - bit7: Block data update
    0 - Continuous update (default)
    1 - Output registers not updated until MSB and LSB have been read which avoids reading values related to different sample times.
    LIS2DH_CTRL4_BLE - bit6: Big/Little endian data selection
    0 - Data LSB at lower address (default)
    1 - Data MSB at lower address
    The BLE function can be activated only in high resolution mode
    LIS2DH_CTRL4_FSCALE_x - bit 4-5: Full-scale selection
    LIS2DH_CTRL4_HR - bit3: Enable high resolution mode
    0 - Normal mode (default)
    1 - High resolution mode
  • Normal mode is only active if CTRL1_LP_EN of register LIS2DH_CTRL1_x and CTRL4_HR are set to 0
  • CTRL4_HR and CTRL1_LP_EN must not be set at the same time
  • LIS2DH_CTRL4_ST_x - bit 1-2: Self test selection
    LIS2DH_CTRL4_SIM - bit0: SPI serial interface mode selection
    0 - 4-wire interface (default)
    1 - 3-wire interface
    SPI mode is currently not supported by this library
    LIS2DH_CTRL4_FSCALE_x:

    Full-scale selection (CTRL4, bit 4-5)

    LIS2DH_CTRL4_FSCALE_2G - (0 << 4): ±2g (default)
    LIS2DH_CTRL4_FSCALE_4G - (1 << 4): ±4g
    LIS2DH_CTRL4_FSCALE_8G - (2 << 4): ±8g
    LIS2DH_CTRL4_FSCALE_16G - (3 << 4): ±16g
    LIS2DH_CTRL4_FSCALE_MSK - (0x03 << 4): Full-scale selection bit mask
    LIS2DH_CTRL4_ST_x:

    Self test selection (CTRL4, bit 1-2)

    LIS2DH_CTRL4_ST_NORMAL - (0 << 1): Normal mode (default)
    LIS2DH_CTRL4_ST_TEST0 - (1 << 1): Self test 0
    LIS2DH_CTRL4_ST_TEST1 - (2 << 1): Self test 1
    LIS2DH_CTRL4_ST_MSK - (0x03 << 1): Self test selection bit mask
    LIS2DH_Init(handle[TLIS2DH_Handle], cs=-1, port, addr=-1)

    Initializes communication with the LIS2DH and prepares the LIS2DH for use


    First of all the device ID is read out.

    Do not use SPI mode. SPI mode is currently not supported by this library.
    handle : TLIS2DH_Handle - Empty device handle for a TLIS2DH
    cs : s32 - Pin used for the CS signal
    -1 - I2C mode enabeld
    >= 0 - Pin used for the CS signal (Only GPIO pins are supported, starting with 0 for the first GPIO of the device)
    port : s32 - interface (SPI or I2C) where LIS2DH is connected to
    The interface must be initialisation before using rM2M_SpiInit() or rM2M_I2cInit().
    addr : s32 - I2C Address of the chip
    -1 - SPI mode enabeld
    >= 0 - I2C Address of the chip (Use only the addresses specified under LIS2DH_I2C_ADRx)
    returns : s32
    OK - if successful
    ERROR - if one of the following errors occurs
  • Interface selection (SPI or IC) is not clear
  • An attempt was made to use SPI mode
  • Found chip not supported by the library
  • < OK - if another error occurs
    LIS2DH_Enable(handle[TLIS2DH_Handle], ctrl1 = LIS2DH_CTRL1_ODR_LP_5_376HZ | LIS2DH_CTRL1_LP_EN | LIS2DH_CTRL1_XYZ_EN, ctrl4 = LIS2DH_CTRL4_BDU | LIS2DH_CTRL4_FSCALE_2G)

    Activates the LIS2DH by setting the "CTRL1" and "CTRL4" register

    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    ctrl1 : s32 - Control register 1 configuration (Output data rate / Power Mode / Axis enable)
    Use LIS2DH_CTRL1_x configuration bits
    ctrl4 : s32 - Control register 4 configuration (Block data update / Full-scale selection / Power Mode / Self Test Enable / SPI Mode selection)
    Use LIS2DH_CTRL4_x configuration bits
    returns : s32
    OK - if successful
    ERROR - if one of the following errors occurs
  • Tryed to activate low power mode and high resultion mode at the same time
  • Invalid Big/Little Endian data selection (The library does not support the Big Endian mode)
  • < OK - if another error occurs
    LIS2DH_ReadMeasurement(handle[TLIS2DH_Handle], &x, &y, &z)

    Reads acceleration data in mg from the LIS2DH

    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    x : s32 - Buffer for storing the X-axis value [mg], unchanged if result < OK
    y : s32 - Buffer for storing the Y-axis value [mg], unchanged if result < OK
    z : s32 - Buffer for storing the Z-axis value [mg], unchanged if result < OK
    returns : s32
    OK - if successful
    ERROR - Unexpected full-scale selection stored in control register 4
    < OK - if another error occurs
    LIS2DH_ReadTemperature(handle[TLIS2DH_Handle], &iTemperature)

    Reads Temperature data in °C from the IS2DH

    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    Temperature : s32 - Variable for storing the temperature [°C], unchanged if result < OK
    returns : s32
    OK - if successful
    < OK - if an error occurs
    LIS2DH_Disable(handle[TLIS2DH_Handle])

    Sets the LIS2DH into power-down mode (i.e. no data sampling is performed) and thus grants minimum power consumption

    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    returns : s32
    OK - if successful
    ERROR - if one of the following errors occurs
  • Control register 1 could not be written
  • Control register 4 could not be written
  • EXPERT

    LIS2DH_I2C_CLOCK_MAX -

    absolute maximum I2C clock speed

    LIS2DH_REG_x:

    Available register (Address | R/W | Default | Description)

    LIS2DH_REG_STATUS_AUX - 0x07 | R | 0x00 |
    Temperature data status register (see LIS2DH_REG_STATUS_AUX_x)
    LIS2DH_REG_OUT_TEMP - 0x0C | R | --- |
    Temperature output data (16-bit Register, use LIS2DH_ReadTemperature())
    Temperature data can be enabled by setting the TEMP_EN bits of the LIS2DH_REG_TEMP_CFG_x (0x1F) register to 1. To retrieve the temperature sensor data BDU bit on LIS2DH_CTRL4_x (0x23) must be set to ‘1’. Temperature data is stored inside LIS2DH_REG_OUT_TEMP as 2’s complement data in 8 bit format left justified. The resolution is 1 LSB/deg and 00h corresponds to 25 degrees Celsius.
    Do not use this register address if BLE bit is set in the LIS2DH_CTRL4_x register. In this case, use LIS2DH_REG_OUT_TEMP_L and LIS2DH_REG_OUT_TEMP_H. Both registers must be read.
    LIS2DH_REG_OUT_TEMP_L - 0x0C | R | --- |
    Temperature output low data (8-bit Register)
    LIS2DH_REG_OUT_TEMP_H - 0x0D | R | --- |
    Temperature output high data (8-bit Register)
    LIS2DH_REG_INT_COUNTER - 0x0E | R | |
    LIS2DH_REG_WHO_AM_I - 0x0F | R | 0x33 |
    Device identification register
    LIS2DH_REG_TEMP_CFG - 0x1F | R/W | |
    Temperature configuration register (see LIS2DH_REG_TEMP_CFG_x)
    LIS2DH_REG_CTRL1 - 0x20 | R/W | 0x07 |
    Control Register 1 (see LIS2DH_CTRL1_x)
    LIS2DH_REG_CTRL2 - 0x21 | R/W | 0x00 |
    Control Register 2 (see LIS2DH_CTRL2_x)
    LIS2DH_REG_CTRL3 - 0x22 | R/W | 0x00 |
    Control Register 3 (see LIS2DH_CTRL3_x)
    LIS2DH_REG_CTRL4 - 0x23 | R/W | 0x00 |
    Control Register 4 (see LIS2DH_CTRL4_x)
    LIS2DH_REG_CTRL5 - 0x24 | R/W | 0x00 |
    Control Register 5 (see LIS2DH_CTRL5_x)
    LIS2DH_REG_CTRL6 - 0x25 | R/W | 0x00 |
    Control Register 6 (see LIS2DH_CTRL6_x)
    LIS2DH_REG_REFERENCE - 0x26 | R/W | 0x00 |
    Reference value for interrupt generation
    LIS2DH_REG_STATUS - 0x27 | R | 0x00 |
    Status data register (see LIS2DH_STATUS_x)
    LIS2DH_REG_OUT_X - 0x28 | R | --- |
    X-axis output acceleration data (16-bit Register, use LIS2DH_ReadMeasurement())
    Acceleration data ist stored as two’s complement date in 8 bit (low power mode), 10 bit (normal mode) or 12 bit (high resolution mode) format left justified.
    Do not use this register address if BLE bit is set in the LIS2DH_CTRL4_x register. In this case, use LIS2DH_REG_OUT_X_L and LIS2DH_REG_OUT_X_L.
    LIS2DH_REG_OUT_X_L - 0x28 | R | --- |
    X-axis output acceleration low data (8-bit Register)
    LIS2DH_REG_OUT_X_H - 0x29 | R | --- |
    X-axis output acceleration high data (8-bit Register)
    LIS2DH_REG_OUT_Y - 0x2A | R | --- |
    Y-axis output acceleration data (16-bit Register, use LIS2DH_ReadMeasurement())
    Acceleration data ist stored as two’s complement date in 8 bit (low power mode), 10 bit (normal mode) or 12 bit (high resolution mode) format left justified.
    Do not use this register address if BLE bit is set in the LIS2DH_CTRL4_x register. In this case, use LIS2DH_REG_OUT_Y_L and LIS2DH_REG_OUT_Y_L.
    LIS2DH_REG_OUT_Y_L - 0x2A | R | --- |
    Y-axis output acceleration low data (8-bit Register)
    LIS2DH_REG_OUT_Y_H - 0x2B | R | --- |
    Y-axis output acceleration high data (8-bit Register)
    LIS2DH_REG_OUT_Z - 0x2C | R | --- |
    Z-axis output acceleration low data (16-bit Register, use LIS2DH_ReadMeasurement())
    Acceleration data ist stored as two’s complement date in 8 bit (low power mode), 10 bit (normal mode) or 12 bit (high resolution mode) format left justified.
    Do not use this register address if BLE bit is set in the LIS2DH_CTRL4_x register. In this case, use LIS2DH_REG_OUT_Z_L and LIS2DH_REG_OUT_Z_L.
    LIS2DH_REG_OUT_Z_L - 0x2C | R | --- |
    Z-axis output acceleration low data (8-bit Register)
    LIS2DH_REG_OUT_Z_H - 0x2D | R | --- |
    Z-axis output acceleration high data (8-bit Register)
    LIS2DH_REG_FIFO_CTRL - 0x2E | R/W | 0x00 |
    FIFO control register (see LIS2DH_FIFO_CTRL_x)
    LIS2DH_REG_FIFO_SRC - 0x2F | R | 0x20 |
    FIFO source register (see LIS2DH_FIFO_SRC_x)
    LIS2DH_REG_INT1_CFG - 0x30 | R/W | 0x00 |
    Interrupt 1 configuration register (see LIS2DH_INT1_CFG_x)
    Content of this register is loaded at boot.
    Write operation at this address is possible only after system boot.
    LIS2DH_REG_INT1_SRC - 0x31 | R | 0x00 |
    Interrupt 1 source register (see LIS2DH_INT1_SRC_x)
    Reading at this address clears LIS2DH_INT2_SRC_INT_ACTIVE bit of LIS2DH_INT1_SRC_x (and the interrupt signal on INT 1 pin) and allows the refreshment of data in the LIS2DH_INT1_SRC_x register if the latched option was chosen.
    LIS2DH_REG_INT1_THS - 0x32 | R/W | 0x00 |
    Interrupt 1 threshold register
    1 LSB = 16mg @full-scale=2g
    1 LSB = 32mg @full-scale=4g
    1 LSB = 62mg @full-scale=8g
    1 LSB = 186mg @full-scale=16g
    LIS2DH_REG_INT1_DURATION - 0x33 | R/W | 0x00 |
    Interrupt 1 duration register:
    Bits 0-6 set the minimum duration of the Interrupt 1 event to be recognized. Duration steps and maximum values depend on the ODR chosen (1 LSB = 1/ODR).
    Duration time is measured in N/ODR, where N is the content of the duration register.
    LIS2DH_REG_INT2_CFG - 0x34 | R/W | 0x00 |
    Interrupt 2 configuration register (see LIS2DH_INT2_CFG_x)
    Content of this register is loaded at boot.
    Write operation at this address is possible only after system boot.
    LIS2DH_REG_INT2_SRC - 0x35 | R | 0x00 |
    Interrupt 2 source register (see LIS2DH_INT2_SRC_x)
    Reading at this address clears LIS2DH_INT2_SRC_INT_ACTIVE bit of LIS2DH_INT2_SRC_x (and the interrupt signal on INT 2 pin) and allows the refreshment of data in the LIS2DH_INT2_SRC_x register if the latched option was chosen.
    LIS2DH_REG_INT2_THS - 0x36 | R/W | 0x00 |
    Interrupt 2 threshold register
    1 LSB = 16mg @full-scale = 2g
    1 LSB = 32mg @full-scale = 4g
    1 LSB = 62mg @full-scale = 8g
    1 LSB = 186mg @full-scale = 16g
    LIS2DH_REG_INT2_DURATION - 0x37 | R/W | 0x00 |
    Interrupt 2 duration register:
    Bits 0-6 set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen (1 LSB = 1/ODR).
    Duration time is measured in N/ODR, where N is the content of the duration register.
    LIS2DH_REG_CLICK_CFG - 0x38 | R/W | 0x00 |
    Click-Click configuration register (see LIS2DH_CLICK_CFG_x)
    LIS2DH_REG_CLICK_SRC - 0x39 | R | 0x00 |
    Click-Click source register (see LIS2DH_CLICK_SRC_x)
    LIS2DH_REG_CLICK_THS - 0x3A | R/W | 0x00 |
    Click-Click threshold register (bits 0-6)
    LIS2DH_REG_TIME_LIMIT - 0x3B | R/W | 0x00 |
    Click-Click time limit register (bits 0-6)
    LIS2DH_REG_TIME_LATENCY - 0x3C | R/W | 0x00 |
    Click-Click time latency register (bits 0-7)
    LIS2DH_REG_TIME_WINDOW - 0x3D | R/W | 0x00 |
    Click-Click time window register (bits 0-7)
    LIS2DH_REG_ACT_THS - 0x3E | R/W | 0x00 |
    Sleep to wake, return to sleep activation threshold in Low power mode (bits 0-6)
    1 LSB = 16mg @full-scale = 2g
    1 LSB = 32mg @full-scale = 4g
    1 LSB = 62mg @full-scale = 8g
    1 LSB = 186mg @full-scale = 16g
    LIS2DH_REG_ACT_DUR - 0x3F | R/W | 0x00 |
    Sleep to wake, return to sleep duration
    1 LSB = (8*1[LSB]+1)/ODR
    LIS2DH_REG_STATUS_AUX_x:

    Temperature data status bits

    LIS2DH_REG_STATUS_AUX_TOR - bit 6: Temperature data overrun
    0 - No overrun has occurred
    1 - New temperature data has overwritten the previous one
    LIS2DH_REG_STATUS_AUX_TDA - bit 2: Temperature new data available
    0 - New temperature data is not yet available
    1 - New temperature data is available
    LIS2DH_REG_TEMP_CFG_x:

    Temperature configuration bits

    LIS2DH_REG_TEMP_CFG_TEMP_x - bit 6-7: Temperature sensor enable
    LIS2DH_REG_TEMP_CFG_TEMP_x:

    Temperature sensor enable (REG_TEMP_CFG, bit 6-7)

    LIS2DH_REG_TEMP_CFG_TEMP_OFF - (0x00): Temperature sensor off
    LIS2DH_REG_TEMP_CFG_TEMP_EN - (0xC0): Temperature sensor enable
    LIS2DH_REG_TEMP_CFG_TEMP_MSK - (0xC0): Temperature sensor enable bit mask
    LIS2DH_CTRL2_x:

    CTRL2 configuration bits

    LIS2DH_CTRL2_HPF_x - bits 6-7: High pass filter mode
    LIS2DH_CTRL2_HPCF2 - bit5: High pass filter cut off frequency selection
    LIS2DH_CTRL2_HPCF1 - bit4: High pass filter cut off frequency selection
    LIS2DH_CTRL2_FPS_EN - bit3: Filtered Data Selection
    0 - internal filter bypassed
    1 - data from internal filter sent to output register and FIFO
    LIS2DH_CTRL2_HPCLICK_EN - bit2: High Pass filter enabled for CLICK function
    0 - filter bypassed
    1 - filter enabled
    LIS2DH_CTRL2_HPIS_INT2_EN - bit1: High Pass filter enabled for AOI function on Interrupt 2
    0 - filter bypassed
    1 - filter enabled
    LIS2DH_CTRL2_HPIS_INT1_EN - bit0: High Pass filter enabled for AOI function on Interrupt 1
    0 - filter bypassed
    1 - filter enabled
    LIS2DH_CTRL2_HPF_x:

    High pass filter modes (CTRL2, bits 6-7)

    LIS2DH_CTRL2_HPF_NORMAL_RST - (0 << 6): Normal mode (reset reading LIS2DH_REG_REFERENCE (0x26) register) (default)
    LIS2DH_CTRL2_HPF_REF_SIGNAL - (1 << 6): Reference signal for filtering
    LIS2DH_CTRL2_HPF_NORMAL - (2 << 6): Normal mode
    LIS2DH_CTRL2_HPF_AUTORESET - (3 << 6): Autoreset on interrupt event
    LIS2DH_CTRL2_HPF_MSK - (0x03 << 6): High pass filter modes bit mask
    LIS2DH_CTRL3_x:

    CTRL3 configuration bits

    LIS2DH_CTRL3_I1_CLICK_EN - bit7: CLICK interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL3_I1_AOI1_EN - bit6: AOI1 interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL3_I1_AOI2_EN - bit5: AOI2 interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL3_I1_DRDY1_EN - bit4: DRDY1 interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL3_I1_DRDY2_EN - bit3: DRDY2 interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL3_I1_WTM_EN - bit2: FIFO watermark interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL3_I1_OVERRUN_EN - bit1: FIFO overrun interrupt on INT1 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL5_x:

    CTRL5 configuration bits

    LIS2DH_CTRL5_BOOT - bit7: Reboot memory content
    0 - Normal mode (default)
    1 - reboot memory content
    LIS2DH_CTRL5_FIFO_EN - bit6: FIFO enable
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL5_LIR_INT1 - bit3: Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC itself
    0 - interrupt request not latched (default)
    1 - interrupt request latched
    LIS2DH_CTRL5_D4D_INT1 - bit2: 4D enable: 4D detection is enabled on INT1 pin if 6D bit on INT1_CFG is set (LIS2DH_INT1_CFG_MODE_x is set to either LIS2DH_INT1_CFG_MODE_6D_MOVE or LIS2DH_INT1_CFG_MODE_6D_POS)
    LIS2DH_CTRL5_LIR_INT2 - bit1: Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself
    0 - interrupt request not latched (default)
    1 - interrupt request latched
    LIS2DH_CTRL5_D4D_INT2 - bit0: 4D enable: 4D detection is enabled on INT2 pin if 6D bit on INT2_CFG is set (LIS2DH_INT2_CFG_MODE_x is set to either LIS2DH_INT2_CFG_MODE_6D_MOVE or LIS2DH_INT2_CFG_MODE_6D_POS)
    LIS2DH_CTRL6_x:

    CTRL6 configuration bits

    LIS2DH_CTRL6_I2_CLICK_EN - bit7: Click interrupt on INT2 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL6_I2_INT1_EN - bit6: Interrupt 1 function enable on INT2 pin
    0 - function disabled (default)
    1 - function enabeld
    LIS2DH_CTRL6_I2_INT2_EN - bit5: Interrupt 2 function enable on INT2 pin
    0 - function disabled (default)
    1 - function enabeld
    LIS2DH_CTRL6_BOOT_I2_EN - bit4: Boot on INT2 pin enable
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL6_P2_ACT - bit3: Activity interrupt enable on INT2 pin
    0 - disabled (default)
    1 - enabeld
    LIS2DH_CTRL6_LOW_ACTIVE - bit1: Interrupt active
    0 - Interrupt active high (default)
    1 - Interrupt active low
    LIS2DH_STATUS_x:

    Status data bits

    LIS2DH_STATUS_ZYXOR - bit7: X-, Y- and Z-axis data overrun
    0 - No overrun has occurred
    1 - A new set of data has overwritten the previous ones
    LIS2DH_STATUS_ZOR - bit6: Z-axis data overrun
    0 - No overrun has occurred
    1 - New data for the Z-axis has overwritten the previous one
    LIS2DH_STATUS_YOR - bit5: Y-axis data overrun
    0 - No overrun has occurred
    1 - New data for the Y-axis has overwritten the previous one
    LIS2DH_STATUS_XOR - bit4: Y-axis data overrun
    0 - No overrun has occurred
    1 - New data for the X-axis has overwritten the previous one
    LIS2DH_STATUS_ZYXDA - bit3: X-, Y- and Z-axis new data available
    0 - A new set of data is not yet available
    1 - A new set of data is available
    LIS2DH_STATUS_ZDA - bit2: Z-axis new data available
    0 - New data for the Z-axis is not yet available
    1 - New data for the Z-axis is available
    LIS2DH_STATUS_YDA - bit1: Y-axis new data available
    0 - New data for the Y-axis is not yet available
    1 - New data for the Y-axis is available
    LIS2DH_STATUS_XDA - bit0: X-axis new data available
    0 - New data for the X-axis is not yet available
    1 - New data for the X-axis is available
    LIS2DH_FIFO_CTRL_x:

    FIFO control bits

    LIS2DH_FIFO_CTRL_MODE_x - bit 6-8: FIFO mode selection
    LIS2DH_FIFO_CTRL_TRIG_INT2_EN - bit5: Trigger selection
    0 - Trigger event allows to trigger signal on INT1 (default)
    1 - Trigger event allows to trigger signal on INT2
    LIS2DH_FIFO_CTRL_FTH4 - bit4:
    0 - (default)
    LIS2DH_FIFO_CTRL_FTH3 - bit3:
    0 - (default)
    LIS2DH_FIFO_CTRL_FTH2 - bit2:
    0 - (default)
    LIS2DH_FIFO_CTRL_FTH1 - bit1:
    0 - (default)
    LIS2DH_FIFO_CTRL_FTH0 - bit0:
    0 - (default)
    LIS2DH_FIFO_CTRL_MODE_x:

    FIFO mode selection (FIFO_CTRL, bit 6-8)

    LIS2DH_FIFO_CTRL_MODE_BYPASS - (0 << 6): Bypass mode (default)
    LIS2DH_FIFO_CTRL_MODE_FIFO - (1 << 6): FIFO mode
    LIS2DH_FIFO_CTRL_MODE_STREAM - (2 << 6): Stream mode
    LIS2DH_FIFO_CTRL_MODE_TRIGGER - (3 << 6): Trigger mode
    LIS2DH_FIFO_CTRL_MODE_MSK - (0x03 << 6): FIFO mode selection bit mask
    LIS2DH_FIFO_CTRL_TRIGGER_x:

    Trigger selection (FIFO_CTRL, bit5)

    LIS2DH_FIFO_CTRL_TRIGGER_INT1 - (0 << 5): Trigger event allows to trigger signal on INT1
    LIS2DH_FIFO_CTRL_TRIGGER_INT2 - (1 << 5): Trigger event allows to trigger signal on INT2
    LIS2DH_FIFO_SRC_x:

    FIFO source bits

    LIS2DH_FIFO_SRC_WTM - bit7
    LIS2DH_FIFO_SRC_OVRN_FIFO - bit6
    LIS2DH_FIFO_SRC_EMPTY - bit5
    LIS2DH_FIFO_SRC_FSS4 - bit4
    LIS2DH_FIFO_SRC_FSS3 - bit3
    LIS2DH_FIFO_SRC_FSS2 - bit2
    LIS2DH_FIFO_SRC_FSS1 - bit1
    LIS2DH_FIFO_SRC_FSS0 - bit0
    LIS2DH_INT1_CFG_x:

    Interrupt 1 configuration bits

    Content of this register is loaded at boot
    Write operation at this address is possible only after system boot.
    LIS2DH_INT1_CFG_MODE_x - bit 6-8; Interrupt mode selection
    LIS2DH_INT1_CFG_Z_HIGH_UP - bit5: Enable interrupt generation on Z high event or on direction recognition
    0 - disable interrupt request (default)
    1 - enable interrupt request
    LIS2DH_INT1_CFG_Z_LOW_DOWN - bit4: Enable interrupt generation on Z low event or on direction recognition
    0 - disable interrupt request (default)
    1 - enable interrupt request
    LIS2DH_INT1_CFG_Y_HIGH_UP - bit3: Enable interrupt generation on Y high event or on direction recognition
    0 - disable interrupt request (default)
    1 - enable interrupt request
    LIS2DH_INT1_CFG_Y_LOW_DOWN - bit2: Enable interrupt generation on Y low event or on direction recognition
    0 - disable interrupt request (default)
    1 - enable interrupt request
    LIS2DH_INT1_CFG_X_HIGH_UP - bit1: Enable interrupt generation on X high event or on direction recognition
    0 - disable interrupt request (default)
    1 - enable interrupt request
    LIS2DH_INT1_CFG_X_LOW_DOWN - bit0: Enable interrupt generation on X low event or on direction recognition
    0 - disable interrupt request (default)
    1 - enable interrupt request
    LIS2DH_INT1_CFG_MODE_x:

    Interrupt mode selection (INT1_CFG, bit 6-8)

    LIS2DH_INT1_CFG_MODE_OR - (0 << 6): OR combination of interrupt events
    LIS2DH_INT1_CFG_MODE_6D_MOVE - (1 << 6): 6 directions movement recognition. An interrupt is generated when orientation move from unknown zone to known zone. The interrupt signal stays for a duration ODR.
    LIS2DH_INT1_CFG_MODE_AND - (2 << 6): AND combination of interrupt events
    LIS2DH_INT1_CFG_MODE_6D_POS - (3 << 6): 6 direction position recognition. An interrupt is generated when orientation is inside a known zone. The interrupt signal stays until orientation is inside the zone.
    LIS2DH_INT1_CFG_MODE_MSK - (0x03 << 6): Interrupt mode selection bit mask
    LIS2DH_INT1_SRC_x:

    Interrupt 1 source bits

    Reading at this address clears LIS2DH_INT2_SRC_INT_ACTIVE bit of INT1_SRC (and the interrupt signal on INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
    LIS2DH_INT1_SRC_INT_ACTIVE - bit6: Interrupt active
    0 - no interrupt has been generated
    1 - one or more interrupts have been generated
    LIS2DH_INT1_SRC_Z_HIGH - bit5: Z high
    0 - no interrupt
    1 - Z high event has occurred
    LIS2DH_INT1_SRC_Z_LOW - bit4: Z low
    0 - no interrupt
    1 - Z low event has occurred
    LIS2DH_INT1_SRC_Y_HIGH - bit3: Y high
    0 - no interrupt
    1 - Y high event has occurred
    LIS2DH_INT1_SRC_Y_LOW - bit2: Y low
    0 - no interrupt
    1 - Y low event has occurred
    LIS2DH_INT1_SRC_X_HIGH - bit1: X high
    0 - no interrupt
    1 - X high event has occurred
    LIS2DH_INT1_SRC_X_LOW - bit0: X low.
    0 - no interrupt
    1 - X low event has occurred
    LIS2DH_INT2_CFG_x:

    Interrupt 2 configuration bits

    Content of this register is loaded at boot
    Write operation at this address is possible only after system boot.
    LIS2DH_INT2_CFG_MODE_x - bit 6-8; Interrupt mode selection
    LIS2DH_INT2_CFG_Z_HIGH - bit5: Enable interrupt generation on Z high event
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_INT2_CFG_Z_LOW - bit4: Enable interrupt generation on Z low event
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value lower than preset threshold
    LIS2DH_INT2_CFG_Y_HIGH - bit3: Enable interrupt generation on Y high event
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_INT2_CFG_Y_LOW - bit2: Enable interrupt generation on Y low event
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value lower than preset threshold
    LIS2DH_INT2_CFG_X_HIGH - bit1: Enable interrupt generation on X high event
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_INT2_CFG_X_LOW - bit0: Enable interrupt generation on X low event
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value lower than preset threshold
    LIS2DH_INT2_CFG_MODE_x:

    Interrupt mode selection (INT2_CFG, bit 6-8)

    LIS2DH_INT2_CFG_MODE_OR - (0 << 6): OR combination of interrupt events
    LIS2DH_INT2_CFG_MODE_6D_MOVE - (1 << 6): 6 directions movement recognition. An interrupt is generated when orientation move from unknown zone to known zone. The interrupt signal stays for a duration ODR.
    LIS2DH_INT2_CFG_MODE_AND - (2 << 6): AND combination of interrupt events
    LIS2DH_INT2_CFG_MODE_6D_POS - (3 << 6): 6 direction position recognition. An interrupt is generated when orientation is inside a known zone. The interrupt signal stays until orientation is inside the zone.
    LIS2DH_INT2_CFG_MODE_MSK - (0x03 << 6): Interrupt mode selection bit mask
    LIS2DH_INT2_SRC_x:

    Interrupt 2 source bits

    Reading at this address clears LIS2DH_INT2_SRC_INT_ACTIVE bit of INT2_SRC (and the interrupt signal on INT 2 pin) and allows the refreshment of data in the INT2_SRC register if the latched option was chosen.
    LIS2DH_INT2_SRC_INT_ACTIVE - bit6: Interrupt active
    0 - no interrupt has been generated
    1 - one or more interrupts have been generated
    LIS2DH_INT2_SRC_Z_HIGH - bit5: Z high
    0 - no interrupt
    1 - Z high event has occurred
    LIS2DH_INT2_SRC_Z_LOW - bit4: Z low
    0 - no interrupt
    1 - Z low event has occurred
    LIS2DH_INT2_SRC_Y_HIGH - bit3: Y high
    0 - no interrupt
    1 - Y high event has occurred
    LIS2DH_INT2_SRC_Y_LOW - bit2: Y low
    0 - no interrupt
    1 - Y low event has occurred
    LIS2DH_INT2_SRC_X_HIGH - bit1: X high
    0 - no interrupt
    1 - X high event has occurred
    LIS2DH_INT2_SRC_X_LOW - bit0: X Low
    0 - no interrupt
    1 - X low event has occurred
    LIS2DH_CLICK_CFG_x:

    Click-Click configuration bits

    LIS2DH_CLICK_CFG_Z_DOUBLE - bit5: Enable interrupt double tap-tap on Z-axis
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_CLICK_CFG_Z_SINGLE - bit5: Enable interrupt single tap-tap on Z-axis
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_CLICK_CFG_Y_DOUBLE - bit5: Enable interrupt double tap-tap on Y-axis
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_CLICK_CFG_Y_SINGLE - bit5: Enable interrupt single tap-tap on Y-axis
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_CLICK_CFG_X_DOUBLE - bit5: Enable interrupt double tap-tap on X-axis
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_CLICK_CFG_X_SINGLE - bit5: Enable interrupt single tap-tap on X-axis
    0 - disable interrupt request (default)
    1 - enable interrupt request on measured accel. value higher than preset threshold
    LIS2DH_CLICK_SRC_x:

    Click-Click source bits

    LIS2DH_CLICK_SRC_INT_ACTIVE - bit6: Interrupt active
    0 - no interrupt has been generated
    1 - One or more interrupts have been generated
    LIS2DH_CLICK_SRC_DOUBLE_CLICK - bit5: Double Click-Click enable
    0 - double Click-Click detection disable
    1 - double tap-tap detection enable
    LIS2DH_CLICK_SRC_SINGLE_CLICK - bit4: Single Click-Click enable
    0 - single Click-Click detection disable
    1 - single Click-Click detection enable
    LIS2DH_CLICK_SRC_SIGN_NEG - bit3: Click-Click sign.
    0 - positive detection
    1 - negative detection
    LIS2DH_CLICK_SRC_Z - bit2: Z Click-Click detection
    0 - no interrupt
    1 - Z high event has occurred
    LIS2DH_CLICK_SRC_Y - bit1: Y Click-Click detection
    0 - no interrupt
    1 - Y high event has occurred
    LIS2DH_CLICK_SRC_X - bit0: X Click-Click detection
    0 - no interrupt
    1 - X high event has occurred
    LIS2DH_Read(handle[TLIS2DH_Handle], iRegInfo, &iData)

    Reads a register of the LIS2DH

    Use this function to read unsigned 8-bit or signed 16-Bit registers of the LIS2DH. The read data is unpacked according to the data type in the register information variable.
    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    iRegInfo : s32 - Register information contains address and data type (Use LIS2DH_REG_x)
    iData : s32 - Variable for storing the data read from the LIS2DH
    returns : s32
    OK - if successful
    < OK - if an error occurs
    LIS2DH_ReadBuf(handle[TLIS2DH_Handle], iRegInfo, aData{}, iLen)

    Reads raw data from a number of LIS2DH registers

    Use this function to read a defined number of registers from the LIS2DH. The data is given back as packed array.
    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    iRegInfo : s32 - Address of the register from which onwards the data should be read (Use LIS2DH_REG_x)
    aData : {} - Byte array for storing the raw data read from the LIS2DH
    iLen : s32 - Number of bytes to be read
    returns : s32
    OK - if successful
    ERROR - Number of bytes to be read >255
    < OK - if another error occurs
    LIS2DH_Write(handle[TLIS2DH_Handle], iRegInfo, iData)

    Writes a register of the LIS2DH

    Use this function to write 8-bit registers of the LIS2DH.
    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    iRegInfo : s32 - Register information contains address and data type (Use LIS2DH_REG_x)
    iData : s32 - Data to be written to the LIS2DH
    returns : s32
    OK - if successful
    < OK - if an error occurs
    LIS2DH_ReadMeasurementRaw(handle[TLIS2DH_Handle], &x, &y, &z)

    Reads raw acceleration data from the LIS2DH

    The function reads and buffers the raw output values of X- Y- and Z-axis. Output data of one axis consists of two bytes. The rM2M_Pack() function provides access to packed data and allows to store the packed values in another variable. This stored data is accessed by reference.
    handle : TLIS2DH_Handle - Device handle of a specific LIS2DH (Initialized by LIS2DH_Init() )
    x : s32 - Buffer for storing the X-axis raw value, unchanged if result < OK
    y : s32 - Buffer for storing the Y-axis raw value, unchanged if result < OK
    z : s32 - Buffer for storing the Z-axis raw value, unchanged if result < OK
    returns : s32
    OK - if successful
    < OK - if an error occurs

    DEBUG

    LIS2DH_Debug_Config:
    To configure debug mode add the following macro to the main.dde file.
    /** * Use this macro to configure the debug mode: * * 0: No debugging * >0: Issues the following information via the console: * -) Error returned by the LIS2DH_ReadReg() function if: * - the LIS2DH could not be Initialized * - the LIS2DH could not be disabled * - the acceleration data could not be read * - the temperature data could not be read * -) Error returned by the LIS2DH_WriteReg () function if: * - the LIS2DH could not be enabled * - the LIS2DH could not be disabled * -) Address of the register and error returned by the LIS2DH Read/Write access function if: * - a register of the LIS2DH could not be written * - a register of the LIS2DH could not be read * - a number of registers could not be read * -) Error returned by the LIS2DH_ReadBuf() function if the raw acceleration data could not be read * */ #define LIS2DH_DEBUG 0

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    LIS2DH - three-axis accelerometer