AD7195 - 2/4-Channel, 24-Bit ∑-Δ ADC
Description
Library for interfacing Analog Devices AD7195 2/4-Channel 24-Bit ∑-Δ ADC.
The AD7195 is a low noise, complete analog front end for high precision measurement applications and contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The AD7195 contains ac excitation, which is used to remove dc-induced offsets from bridge sensors.
Features:
- SPI interface with communication speed up to 5 MHz
- AC or DC sensor excitation
- Up to 22.5 noise-free bits (gain = 1)
- 2 differential/4 pseudo differential input channels
- Programmable gain (1 to 128)
OVERVIEW
AD7195_Abstract:
This library can be used to handle Analog Devices AD7195 2/4-Channel 24-Bit ∑-Δ ADC.
Interfaces:1x SPI 1x GPIO
The AD7195 is a low noise, complete analog front end for high precision measurement applications and contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low
noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The
AD7195 contains ac excitation, which is used to remove dc-induced offsets from bridge sensors.SPI interface with communication speed up to 5 MHz AC or DC sensor excitation Up to 22.5 noise-free bits (gain = 1) 2 differential/4 pseudo differential input channels Programmable gain (1 to 128)
AD7195_How_to_use:
/* Hardware setup */
const
{
PORT_SPI = 0, // The first SPI interface should be used.
PIN_CS = 0, // The first GPIO should be used for the CS signal
}
/* Handles for available sensors */
new hADC[TAD7195_Handle]; // Handle to manage the AD7195
main()
{
new iStatus; // Status read from the AD7195
// inits the SPI interface
catch(rM2M_SpiInit(PORT_SPI, AD7195_SPICLK, AD7195_SPIMODE));
// Initializes SPI communication with the AD7195
catch (AD7195_Init(hADC, PIN_CS, PORT_SPI));
// Reads the current status from the AD7195
AD7195_Read(hADC, AD7195_REG_STATUS, iStatus);
// Issues the current status via the watch panel
#watch("status=Current Status: %02x", iStatus);
}
BASIC
AD7195_SPICLK -
typical SPI clock speed to be used
AD7195_SPIMODE -
configuration of clock polarity and clock phase for the AD7195
AD7195_Init(handle[TAD7195_Handle], cs, spi)
Initializes SPI communication with the AD7195
First of all the CS port and SPI interface are copied to the transferred device handle. The used CS pin is configured as output and set to high to avoid data transfer at the beginning. Then the AD7195 is reset by writing 40-Bits consecutive 1s to the SPI interface. Afterwards the ID and configuration register are checked to ensure that the AD7195 was initialised correctly
handle : TAD7195_Handle - Empty device handle for a AD7195
cs : s32 - Pin used for the CS signal (Only GPIO pins are supported, starting with 0 for the first GPIO of the device)
spi : s32 - SPI interface where AD7195 is connected to
The SPI interface must be initialisation before using rM2M_SpiInit().
returns : s32
OK - if successful
ERROR - if one of the following errors occurs
< OK - if another error occurs
EXPERT
AD7195_SPICLK_MAX -
absolute maximum SPI clock speed (5MHz)
AD7195_REG_x:
Available register (Address | R/W | Default | Description)
AD7195_REG_COM - 0x00 | W | 0x00 |
Communications Register During a Write Operation (see AD7195_COM_x)
The write operation to the communications register which is necessary for each access to the AD7195 is done by the AD7195_Read() and the AD7195_Write()
functions. Therefore, the user should not need this register
AD7195_REG_STATUS - 0x00 | R | 0x80 |
Status Register During a Read Operation (Ready Bit for ADC, ADC Error Bit, No external reference bit, Parity bit for the data register, which channel is being
converted by the ADC, see AD7195_STATUS_x )
AD7195_REG_MODE - 0x01 | R/W | 0x080060 |
Mode Register (operating mode, output data rate, and clock source, see AD7195_MODE_x)
Any write to the setup register resets the modulator and filter and sets the NRDY bit.
AD7195_REG_CONFIG - 0x02 | R/W | 0x000117 |
Configuration Register ( unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel, see AD7195_CFG_x )
AD7195_REG_DATA - 0x03 | R | 0x000000 |
The conversion result from the ADC is stored in this data register. On completion of a read operation from this register, the NRDY bit/pin is set. When the DAT_STA bit in the mode register is set to 1, the contents
of the status register are appended to each 24-bit conversion. This is advisable when several analog input
channels are enabled because the three LSBs of the status register (CHD2 to CHD0) identify the channel from
which the conversion originated.
AD7195_REG_ID - 0x04 | R | 0xA6 |
ID Register (Identification number for the AD7195)
AD7195_REG_GPOCON - 0x05 | R/W | 0x00 |
GPOCON Regsiter (open or close the bridge power-down switch, see AD7195_GPOCON_x)
AD7195_REG_OFFSET - 0x06 | R/W | 0x800000 |
Each analog input channel has a dedicated offset register that holds the offset calibration coefficient for the channel.
The AD7195 must be in idle mode or power-down mode when writing to the offset register.
AD7195_REG_FS - 0x07 | R/W | 0x5XXXX0 |
The full-scale register holds the full-scale calibration coefficient for the ADC. The AD7195 has4 full-scale registers, each channel having a dedicated full-scale register.
The AD7195 must be in idle mode or power-down mode when writing to the full-scale register.
AD7195_COM_x:
Communications register configuration bits
AD7195_COM_WEN - bit7: Write Enable Bit
0 - Write to the communications register actually occurs (default)
1 - Stays at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next seven bits are loaded to the communications register.
AD7195_COM_WRITE - bit6 (0): The next operation is a write to a specified register (default)
AD7195_COM_READ - bit6 (1): The next operation is a read to a specified register
AD7195_COM_RSx - bit 3-5: Register Address Bits (use "AD7195_REG_x & AD7195_ADDR_MSK").
AD7195_COM_CREAD - bit2: Continuous Read of the Data Register.
0 - Exit the continuous read mode (default)
1 - (And the data register is selected) The serial interface is configured so that the data register can be continuously read.
AD7195_COM_CR1 - bit1: Must be 0 for correct operation (i.e. do not use).
AD7195_COM_CR0 - bit0: Must be 0 for correct operation (i.e. do not use).
AD7195_COM_DEFAULT - (0x00): Default state of the register
AD7195_STATUS_x:
Status Register register bits
AD7195_STATUS_NRDY - bit7: Ready Bit for ADC.
0 - Cleared when data is written to the ADC data register.
1 - Set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user
that the conversion data should not be read. It is also set when the part is placed
in power-down mode or idle mode or when SYNC is taken low.
AD7195_STATUS_ERR - bit6: ADC Error Bit
0 - Cleared when the result written to the data register is within the allowed analog input range again.
1 - Set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s
AD7195_STATUS_NOREF - bit5: No external reference bit
0 - Cleared to indicate that a valid reference is applied to the selected reference pin
1 - Set to indicate that the reference is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s.
This bit is enabled by setting the AD7195_CFG_REFDET bit in the configuration register
AD7195_STATUS_PARITY - bit4: Parity check of the data register
0 - Cleared if there is an even number of 1s in the data register.
1 - Set if there is an odd number of 1s in the data register
This bit is enabled by setting the AD7195_MODE_ENPAR bit in the mode register
AD7195_STATUS_SR3 - bit3: Reserved: Always reads 0
AD7195_STATUS_CH_x - bit 0-2: Indication which channel is being converted by the ADC
AD7195_STATUS_DEFAULT - (0x80): Default state of the register
AD7195_STATUS_CH_x:
Indication which channel is being converted by the ADC (Status Register, bit 0-2)
Positive Input | Negative Input
AD7195_STATUS_CH_AIN1_AIN2 - (0x00): AIN1 | AIN2
AD7195_STATUS_CH_AIN3_AIN4 - (0x01): AIN3 | AIN4
AD7195_STATUS_CH_TEMP - (0x02): Temperature sensor
AD7195_STATUS_CH_AIN2_AIN2 - (0x03): AIN2 | AIN2
AD7195_STATUS_CH_AIN1_AINCOM - (0x04): AIN1 | AINCOM
AD7195_STATUS_CH_AIN2_AINCOM - (0x05): AIN2 | AINCOM
AD7195_STATUS_CH_AIN3_AINCOM - (0x06): AIN3 | AINCOM
AD7195_STATUS_CH_AIN4_AINCOM - (0x07): AIN4 | AINCOM
AD7195_STATUS_CH_MSK - (0x07): Channel Selection bit mask
AD7195_MODE_x:
Mode Register configuration bits (operating mode, output data rate and clock source)
AD7195_MODE_MD_x - bit 21-23: Operating mode
AD7195_DAT_STA - bit20: Bit to enable the transmission of status register contents along with each data register read.
0 - Disabled (default)
1 - Enabled
This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds.
AD7195_MODE_CLK_x - bit 18-19: Clock source
AD7195_MODE_MR16_MR17_MSK - bit 16-17: Must be 0 for correct operation (i.e. do not use).
AD7195_MODE_SINC3 - bit15: Sinc3 filter select bit.
0 - Sinc4 filter is used (default)
1 - Sinc3 filter is used
The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time.
AD7195_MODE_MR14 - bit14: Must be 0 for correct operation (i.e. do not use).
AD7195_MODE_ENPAR - bit13: Enable parity bit.
0 - Parity checking disabled (default)
1 - Parity checking on the data register is enabled
The DAT_STA bit should be set when the parity check is used
AD7195_MODE_MR12 - bit12: Must be 0 for correct operation (i.e. do not use).
AD7195_MODE_SINGLE - bit11: Single cycle conversion enable bit.
0 - Single cycle conversion disabled (default)
1 - The AD7195 settles in one conversion cycle so that it functions as a zero-latency ADC
This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected.
AD7195_MODE_REJ60 - bit10: This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz.
0 - Disabled (default)
1 - A filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection.
AD7195_MODE_FS_x - bit 0-9: Filter output data rate select bits.
AD7195_MODE_MD_x:
Operating mode (Mode Register, bit 13-15 )
AD7195_MODE_MD_CONT_CONV - (0x000000 << 21): Continuous conversion mode (default)
In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register.
AD7195_MODE_MD_SINGLE_CONV - (0x000001 << 21): Single conversion mode
The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC
returns to power-down mode.
AD7195_MODE_MD_IDLE - (0x000002 << 21): Idle mode
In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided.
AD7195_MODE_MD_POWER_DOWN - (0x0003 << 21): Power-down mode
In power-down mode, all circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7195 for settling reasons.
The external crystal, if selected, remains active.
AD7195_MODE_MD_INT_ZS_CALIB - (0x000004 << 21): Internal zero-scale calibration
AD7195_MODE_MD_INT_FS_CALIB - (0x000005 << 21): Internal full-scale calibration
AD7195_MODE_MD_SYS_ZS_CALIB - (0x000006 << 21): System zero-scale calibration
AD7195_MODE_MD_SYS_FS_CALIB - (0x000007 << 21): System full-scale calibration
AD7195_MODE_MD_MSK - (0x000007 << 21): Operating mode bit mask
AD7195_MODE_CLK_x:
Clock source (Mode Register, bit 18-19 )
AD7195_MODE_CLK_EXT_MCKL1_MCLK2 - (0x0000 << 18): External crystal. The external crystal is connected from MCLK1 to MCLK2.
AD7195_MODE_CLK_EXT_MCLK2 - (0x0001 << 18): External clock. The external clock is applied to the MCLK2 pin.
AD7195_MODE_CLK_INT - (0x0002 << 18): Internal 4.92 MHz clock. Pin MCLK2 is tristated. (default)
AD7195_MODE_CLK_INT_CLK_OUT - (0x0003 << 18): Internal 4.92 MHz clock. The internal clock is available on MCLK2.
AD7195_MODE_CLK_MSK - (0x0003 << 18): Clock source bit mask
AD7195_MODE_FS_x:
Filter output data rate (Mode Register, bit 0-9 )
The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise
(and, therefore, the effective resolution) of the device.
When chop is disabled and continuous conversion mode is selected Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel.
When chop is enabled Output Data Rate = (MCLK/1024)/(N × FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2).
Use values in the range 1 to 1023 or the defines for Bit FS0 to FS9. Default value: 96
AD7195_MODE_FS_FS9 - (0x000020): Bit9 (512)
AD7195_MODE_FS_FS8 - (0x000010): Bit8 (256)
AD7195_MODE_FS_FS7 - (0x000080): Bit7 (128)
AD7195_MODE_FS_FS6 - (0x000040): Bit6 (64)
AD7195_MODE_FS_FS5 - (0x000020): Bit5 (32)
AD7195_MODE_FS_FS4 - (0x000010): Bit4 (16)
AD7195_MODE_FS_FS3 - (0x000008): Bit3 (8)
AD7195_MODE_FS_FS2 - (0x000004): Bit2 (4)
AD7195_MODE_FS_FS1 - (0x000002): Bit1 (2)
AD7195_MODE_FS_FS0 - (0x000001): Bit0 (1)
AD7195_MODE_FS_FILTER_MSK - (0x003FF): Filter output data rate bit mask
AD7195_CFG_x:
Configuration Register configuration bits ( unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel)
AD7195_CFG_CHOP - bit23: Chop enable bit
0 - Chop is disabled. Higher conversion rates are allowed. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. (default)
1 - Chop is enabled. The offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC.
When ax excitation is enabled, chop must be enabled also.
AD7195_CFG_ACX - bit22: AC excitation enable bit.
0 - DC-excited input (default)
1 - The signal source to the AD7195 is AC excited
CHOP must be set to 1 when ac excitation is enabled.
AD7195_CFG_CON16_CON21_MSK - bit 16-21: Must be 0 for correct operation (i.e. do not use).
AD7195_CFG_CHx - bit 8-15: Channel select bits
AD7195_CFG_BURN - bit7: Burnout Current Enable Bit.
0 - The burnout currents are disabled (default)
1 - The 500 nA current sources in the signal path are enabled.
The burnout currents can be enabled only when the buffer is active and when chop is disabled.
AD7195_CFG_REFDET - bit6: Enables the reference detect function.
0 - Disabled (default)
1 - The NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum.
The reference detect circuitry operates only when the ADC is active.
AD7195_CFG_CON5 - bit5: Must be 0 for correct operation (i.e. do not use).
AD7195_CFG_BUF - bit4: Enables the buffer on the analog inputs
0 - The analog inputs are unbuffered, lowering the power consumption of the device.
1 - The analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. (default)
With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. When the buffer is enabled, it requires some headroom; therefore, the voltage
on any input pin must be limited to 250 mV within the power supply rails.
AD7195_CFG_UB - bit3: Polarity select bit.
0 - Bipolar operation is selected (default)
1 - Unipolar operation is selected
AD7195_CFG_GAIN_x - bit 0-3: Gain select bits
AD7195_CFG_CHx:
Channel select bits (Configuration Register, bit 8-15)
Used to select which channels are enabled. Several channels can be selected, and the AD7195 automatically sequences them. The conversion on each channel requires the complete
settling time. When performing calibrations or when accessing the calibration registers,
only one channel can be selected.
AD7195_CFG_CH7 - bit15: Channel AIN4 AINCOM
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH6 - bit14: Channel AIN3 AINCOM
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH5 - bit13: Channel AIN2 AINCOM
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH4 - bit12: Channel AIN1 AINCOM
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH3 - bit11: Channel AIN2 AIN2
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH2 - bit10: Channel Temperatur Sensor
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH1 - bit9: Channel AIN3 AIN4
0 - Disabled (default)
1 - Enabled
AD7195_CFG_CH0 - bit8: Channel AIN1 AIN2
0 - Disabled
1 - Enabled (default)
AD7195_CFG_CH_MSK - (0x00FF00): Channel Selection bit mask
AD7195_CFG_GAIN_x:
Gain Select Bits (Configuration Register, bit 0-2)
Gain | ADC Input Range (5 V Reference)
AD7195_CFG_GAIN_1 - (0x000000): 1 | ±5V
AD7195_CFG_GAIN_8 - (0x000003): 8 | ±625 mV
AD7195_CFG_GAIN_16 - (0x000004): 16 | ±312.5 mV
AD7195_CFG_GAIN_32 - (0x000005): 32 | ±156.2 mV
AD7195_CFG_GAIN_64 - (0x000006): 64 | ±78.125 mV
AD7195_CFG_GAIN_128 - (0x000007): 128 | ±39.06 mV (default)
AD7195_CFG_GAIN_MSK - (0x000007): Gain Selection bit mask
AD7195_GPOCON_x:
GPOCON Register configuration bits (open or close the bridge power-down switch)
AD7195_GPOCON_GP7 - bit7: Must be 0 for correct operation (i.e. do not use).
AD7195_GPOCON_BPDSW - bit6: Bridge power-down switch control bit.
0 - The bridge power-down switch is open (default)
1 - The bridge power-down switch BPDSW to AGND is closed. The switch can sink up to 30 mA.
When the ADC is placed in power-down mode, the bridge power-down switch remains active.
AD7195_GPOCON_GP0_GP5_MSK - bit 0-5: Must be 0 for correct operation (i.e. do not use).
AD7195_Read(handle[TAD7195_Handle], iAddress, &iData)
Reads register of AD7195
Use this function to read unsigned 8-Bit, or unsigned 24-Bit registers of the AD7195. The read data is unpacked according to the data type in the register information variable.
handle : TAD7195_Handle - Device handle of a specific AD7195 (Initialized by AD7195_Init() )
iAddress : s32 - Register information contains address and data type (use AD7195_REG_x)
iData : s32 - Variable for storing the data read from the AD7195
returns : s32
OK - if successful
ERROR - The data type contained in iAddress is invalid
< OK - if another error occurs
AD7195_Write(handle[TAD7195_Handle], iAddress, iValue)
Writes register of AD7195
Use this function to write unsigned 8-Bit or unsigned 24-Bit registers of the AD7195. The data to be written is packed according to the data type in the register information variable and sent to the AD7195.
handle : TAD7195_Handle - Device handle of a specific AD7195 (Initialized by AD7195_Init() )
iAddress : s32 - Register information contains address and data type (use AD7195_REG_x)
iValue : s32 - Data to be packed and written to the AD7195
returns : s32
OK - if successful
ERROR - The data type contained in iAddress is invalid
< OK - if another error occurs